MPC5200B Freescale Semiconductor, Inc, MPC5200B Datasheet
MPC5200B
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MPC5200B Summary of contents
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... MPC5200B incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded e300 core. The MPC5200B contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six © Freescale Semiconductor, Inc., 2006. All rights reserved. ...
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... Version 4 ATA compatible external interface—IDE Disk Drive connectivity • BestComm DMA subsystem — Intelligent virtual DMA Controller — Dedicated DMA channels to control peripheral reception and transmission — Local memory (SRAM 16 kBytes SPI, CAN, J1850, Timers, and GPIOs MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor ...
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... Systems Protection (watch dog timer, bus monitor) — Individual control of functional block clock sources — Power management: Nap, Doze, Sleep, Deep Sleep modes — Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN) Freescale Semiconductor 2 C) MPC5200B Data Sheet, Rev. 1 Features 2 S and AC97 3 ...
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... Features • Test/Debug features — JTAG (IEEE 1149.1 test access port) — Common On-chip Processor (COP) debug port • On-board PLL and clock generation Figure 1 shows a simplified MPC5200B block diagram. 4 MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor ...
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... Figure 1. Simplified Block Diagram—MPC5200B Freescale Semiconductor BestComm DMA SRAM 16K MPC5200B Data Sheet, Rev. 1 Features MSCAN 2x J1850 USB 2x SPI Ethernet PSC 6x 5 ...
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... Electrical and Thermal Characteristics 3 Electrical and Thermal Characteristics 3.1 DC Electrical Characteristics 3.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5200B DC Electrical characteristics. maximum ratings. Characteristic Supply voltage - e300 core and peripheral logic Supply voltage - I/O buffers Supply voltage - System APLL Supply voltage - e300 APLL ...
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... Maximum e300 core operating frequency is 400 MHz. 3 Maximum e300 core operating frequency is 266 MHz. 3.1.3 DC Electrical Specifications Table 3 gives the DC Electrical characteristics for the MPC5200B at recommended operating conditions (see Table 2). Characteristic Input high voltage VDD_IO/VDD_MEM_IO Input high voltage Input high voltage ...
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... Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. Table 4. Drive Capability of MPC5200B Output Pins Driver Type Supply Voltage DRV4 VDD_IO = 3 ...
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... Power Dissipation Power dissipation of the MPC5200B is caused by 3 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can ...
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... IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V. 9 Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO 10 Table 6. Power Dissipation Core Power Supply (VDD_CORE) 33/132/66/132/396 Typ 1080 600 225 225 52.5 Typ 2 Typ 33 MPC5200B Data Sheet, Rev. 1 SpecID Unit Notes (1),(2) mW D5.1 (1),(3) mW D5.2 (1),(4) mW D5.3 (1),(5) mW D5.4 (1),( ...
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... R θJA R θJMA R θJMA R θJMA R θJB R θJC Ψ can be obtained from the following equation: J × +( θ MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Unit Notes SpecID (1),(2) 30 °C/W D6.1 (1),(3) 22 °C/W D6.2 (1),(3) 24 °C/W D6.3 (1),(3) 19 °C/W D6.4 (4) 14 °C/W D6.5 (5) 8 °C/W D6 ...
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... Oscillator and PLL Electrical Characteristics The MPC5200B System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent Real-Time Clock (RTC) system. ...
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... The MPC5200B clock generation uses two phase locked loop (PLL) blocks. • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. ...
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... Table 12. • USB • SPI • MSCAN 2 • • J1850 • PSC • GPIOs and Timers • IEEE 1149.1 (JTAG) AC Specifications MPC5200B Data Sheet, Rev. 1 Max Unit SpecID — 550 MHz O4.1 — 40.0 ns O4.2 — 1200 MHz O4.3 — 367 MHz O4.4 — ...
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... VDD_IO = 3.0 to 3.6 V • Input conditions: All Inputs: tr, tf < • Output Loading: All Outputs 3.3.1 AC Operating Frequency Data Table 12 provides the operating frequency information for the MPC5200B. 1 e300 Processor Core 2 SDRAM Clock 3 XL Bus Clock 4 IP Bus Clock 5 PCI / Local Plus Bus Clock ...
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... HRESET - Hard Reset • SRESET - Software Reset These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section. Name Description PORRESET ...
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... SRESET fall time SRESET rise time NOTES: Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter to prevent them from getting into the chip. HRESET and SRESET must have a monotonous rise time. The assertion of HRESET becomes active at Power on Reset without any SYS_XTAL clock. ...
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... PORRESET. This may cause problems because it may change the internal clock ratios and so extend the PLL locking process. 3.3.4 External Interrupts The MPC5200B provides three different kinds of external interrupts: • Four IRQ interrupts • Eight GPIO interrupts with simple interrupt capability (not available in power-down mode) • ...
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... GPIO_IRDA_0 NOTES: 1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200B User Manual [1]. 2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies. ...
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... Min 7.5 — t *0.5 mem_clk — t *0.25-0.7 mem_clk — 0.2 t hold NOP READ NOP DM DM valid hold data setup t hold Column t hold MPC5200B Data Sheet, Rev. 1 Max Units — *0.5+0.4 ns mem_clk — *0.25+0.4 ns mem_clk — ns 0.3 ns — ns NOP NOP NOP NOP data hold Freescale Semiconductor SpecID A5 ...
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... NOP WRITE NOP DM DM hold valid data data valid hold t hold Column t hold MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Max Units — *0.5+0.4 ns mem_clk — *0.25+0.4 ns mem_clk — *0.75+0.4 ns mem_clk — ns NOP NOP NOP ...
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... MEM_CLK t Control Signals, Address and MBA hold hold after rising edge of MEM_CLK data Setup time relative to MDQS setup data Hold time relative to MDQS hold 22 Min 7.5 — t *0.5 mem_clk — MPC5200B Data Sheet, Rev. 1 Max Units SpecID — ns A5.15 t *0.5+0.4 ns A5.16 mem_clk — ns A5.17 0.4 ns A5.18 — ...
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... Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing Freescale Semiconductor t hold NOP READ NOP NOP t data_valid_min t data_sample_min t data_valid_min t 0.5 * MEM_CLK t hold Column t hold MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics NOP NOP NOP t data_valid_max Sample position A t data_sample_max t data_valid_max Sample position B t data_sample_min t data_sample_max 23 ...
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... Parameters apply at the package pins, not at expansion board edge connectors. The MPC5200B is always the source of the PCI CLK. The clock waveform must be delivered to each 33-MHz or 66-MHz PCI component in the system. ...
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... Figure 9. Table 23. PCI Timing Parameters 66 MHz 33 MHz Min Max Min 10, MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics 0.4Vcc, p-to-p (minimum) Units Notes SpecID Max (1),(3) ns A6.1 ns A6.2 ns A6.3 (2) 4 V/ns A6.4 Units Notes SpecID Max (1),(2),( ...
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... Local Plus Bus The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz. ...
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... IPB clocks by an other modules. Freescale Semiconductor Min Max 0 (DC+1)*t t PCIck - t PCIck - 6 PCIck PCIck t IPBIck t IPBIck - 2.0 - 4.4 MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Units Notes SpecID (6) ns A7.13 PCIck ( A7.14 (3) ns A7.15 (4) ns A7.16 (4) ns A7.17 ( A7.18 ...
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... Table 25. Burst Mode Timing Min 4.6 2.9 LB (1+WS+4 *2*(32/DS))* (1+WS+4 t PCIck t IPBIck -0 PCIck t PCIck MPC5200B Data Sheet, Rev Max Units Notes SpecID 10.6 ns A7.22 7.0 ns A7.23 LB (1),(2) *2*(32/DS)) ns A7.24 *t PCIck t ns A7.25 PCIck - ns A7.26 4 ...
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... Table 25. Burst Mode Timing (continued) Min 3 *2*(32/DS)*t PCIck - t PCIck Figure 12. Timing Diagram—Burst Mode MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Max Units Notes SpecID - (4) (DC+1)*t ns PCIck (WS+1)*t ns PCIck (3) 7 (2),(3) 4 *2*(32/DS)*t ns PCIck 2 ...
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... IPB clocks by an other modules. 30 Table 26. MUXed Mode Timing Min Max 4.6 10.6 2.9 7.0 - 3.6 - 5.7 - -1.2 - -1.2 t IPBIck 8.5 0 (DC+1)* PCIck - 6 PCIck (2+WS)*t (2+WS)*t PCIck - 4.7 - 5.9 t IPBIck - t PCIck t IPBIck - t PCIck - t PCIck - 2.0 - 4.4 MPC5200B Data Sheet, Rev. 1 Units Notes SpecID ns A7.39 ns A7.40 ns A7.41 ns A7.42 ns A7.43 ns A7. A7. A7.46 (1),(3) ns A7.47 PCIck ns A7.48 ns A7.49 ns A7.50 ns A7.51 PCIck ns A7.52 ns A7. A7.54 ns A7.55 ( A7.56 (2) ns A7.57 ns A7.58 ( ...
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... ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200B User Manual [1]. The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes. ...
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... The MPC5200B operating frequency (IP bus clock frequency) • Internal MPC5200B bus latencies • Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User Manual [1]. All output timing numbers are specified for nominal 50 pF loads. Sym PIO Timing Parameter ...
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... MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Mode 1(ns) Mode 2(ns) SpecID 150 120 A8.12 — — A8. ...
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... Data valid hold time at sender, from STROBE edge. 200 0 170 First STROBE time for drive to first negate DSTROBE from STOP during a data-in burst. 150 0 150 Limited Interlock time. — 20 — Interlock time with minimum. MPC5200B Data Sheet, Rev Comment SpecID A8.26 A8.27 A8.28 A8.29 A8.30 A8 ...
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... Setup and hold times for DMACK, before assertion or negation. — 50 — Time from STROBE edge to negation of DMARQ or assertion of STOP, when sender terminates a burst. after negation of DMARDY. Both STROBE and DMARDY timing measurements RFS MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Comment SpecID A8.35 A8.36 A8.37 A8.38 A8.39 A8 ...
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... Figure 17. Timing Diagram—Sustained Ultra DMA Data In Burst ACK ENV t ZAD t t ACK ENV t ZAD t ZIORDY ACK t 2CYC t t CYC CYC t t DVS DVH MPC5200B Data Sheet, Rev DVS DVH t 2CYC t t DVS DVH t DH Freescale Semiconductor ...
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... HDMARDY (host DSTROBE (device) DD[0:15] DA0,DA1,DA2, CS[0:1] Figure 19. Timing Diagram—Drive Terminating Ultra DMA Data In Burst Freescale Semiconductor RFS MLI ZAH t DVS t AZ MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics t ACK t ACK t IORDYZ t DVH CRC t ACK 37 ...
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... DA0,DA1,DA2, CS[0:1] Figure 21. Timing Diagram—Initiating an Ultra DMA Data Out Burst ZAH ENV t ACK ZIORDY t ACK t ACK MPC5200B Data Sheet, Rev MLI t ACK t ACK t MLI t IORDYZ t DVS t DVH CRC t ACK DVS t DVH Freescale Semiconductor ...
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... DDMARDY (device) HSTROBE DD[0:15] (host) Figure 23. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst Freescale Semiconductor t 2CYC t t CYC CYC t DVS t DVH RFS MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics t 2CYC t DVS t DVH ...
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... DD[0:15] (host) DA0,DA1,DA2, CS[0:1] Figure 25. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst DVS RFS LI MPC5200B Data Sheet, Rev MLI t ACK t IORDYZ t ACK t DVH CRC t ACK t t MLI ACK t IORDYZ t t MLI ACK ...
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... RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6]. Freescale Semiconductor Table 30. Timing Specification ata_isolation 1 Figure 26. Timing Diagram-ATA-ISOLATION Table 31. MII Rx Signal Timing Min 10 10 35% 35% MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Min Max Units Bus cycles - 19 IP Bus cycles ...
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... Table 32. MII Tx Signal Timing Min 5 — 35% 35 Table 33. MII Async Signal Timing Min 1.5 MPC5200B Data Sheet, Rev. 1 Max Unit SpecID — A9.6 (1) 65% TX_CLK Period A9.7 (1) 65% TX_CLK Period A9.8 Max Unit SpecID — TX_CLK Period A9 ...
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... NOTES: 1 MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5200B User Manual [1]. 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register ...
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... Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode). Output timing is specified at a nominal 50 pF load. 2 USB_OE USB_TXN 1 USB_TXP Figure 31. Timing Diagram—USB Output Line 44 Description NOTE MPC5200B Data Sheet, Rev. 1 Min Max Units SpecID 83.3 667 ns 83.3 667 ns — 7.9 ns — 7.9 ns Freescale Semiconductor A10 ...
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... Input Data hold time 8 Slave disable lag time 9 Sequential transfer delay 10 Clock falling time 11 Clock rising time NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1]. Output timing is specified at a nominal 50 pF load. SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output ...
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... Output Data valid after SCK 6 Input Data setup time 7 Input Data hold time 8 Slave disable lag time 9 Sequential Transfer delay NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1]. Output timing is specified at a nominal 50 pF load. SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input ...
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... Input Data hold time 7 Slave disable lag time 8 Sequential Transfer delay 9 Clock falling time 10 Clock rising time NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1]. Output timing is specified at a nominal 50 pF load. SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output ...
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... Output data valid 5 Input Data setup time 6 Input Data hold time 7 Slave disable lag time 8 Sequential Transfer delay NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1]. Output timing is specified at a nominal 50 pF load. SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input ...
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... Clock high time 7 Data setup time 8 Start condition setup time (for repeated start condition only) 9 Stop condition setup time NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1]. Table 41. I Sym (1) 1 Start condition hold time (1) 2 Clock low time (2) 3 SCL/SDA rise time ...
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... Electrical and Thermal Characteristics 2 SCL 1 SDA Figure 36. Timing Diagram—I 3.3.14 J1850 See the MPC5200B User Manual [1]. 3.3.15 PSC 3.3.15.1 Codec Mode (8,16,24 and 32-bit Table 42. Timing Specifications—8,16, 24, and 32-bit CODEC / I Sym Description 1 Bit Clock cycle time, programmed in CCS register 2 Clock duty cycle 3 Bit Clock fall time ...
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... Bit Clock cycle time Output timing is specified at a nominal 50 pF load. Freescale Semiconductor Min 40.0 1.0 1.0 1.0 NOTE MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics 2 S Master Mode 2 S Slave Mode Typ Max Units — — ns (1) — 50 — % — ...
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... Output Data valid after rising clock edge 6 Input Data setup time 7 Input Data hold time Output timing is specified at a nominal 50 pF load Min 1.0 1.0 NOTE MPC5200B Data Sheet, Rev Slave Mode Typ Max Units — 81.4 — ns — 40.7 — ns — 40.7 — ...
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... Figure 40. Timing Diagram — IrDA Transmit Line Freescale Semiconductor Figure 39. Timing Diagram — AC97 Mode Description NOTE MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Min Max Units SpecID µs 0.125 10000 A15.22 µs 0.125 10000 A15.23 — ...
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... SS Output 4 MOSI Output 6 MISO Input Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) 54 Description NOTE MPC5200B Data Sheet, Rev. 1 Min Max Units SpecID 30.0 — ns A15.26 15.0 — ns A15.27 30.0 — ns A15.28 — 8.9 ns A15.29 — 8.9 ns A15.30 6.0 — ...
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... Input 3 SS Input 4 MOSI Input 6 MISO Output Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Freescale Semiconductor Description NOTE MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Min Max Units SpecID 30.0 — ns A15.37 15.0 — ns A15.38 1.0 — ns A15.39 1.0 — ...
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... Output 3 SS Output 4 MOSI Output MISO Input Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) 56 Description NOTE MPC5200B Data Sheet, Rev. 1 Min Max Units SpecID 30.0 — ns A15.46 15.0 — ns A15.47 30.0 — ns A15.48 — 8.9 ns A15.49 6.0 — ...
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... Input 3 SS Input MOSI Input 4 MISO Output Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) Freescale Semiconductor Description NOTE MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Min Max Units SpecID 30.0 — ns A15.56 15.0 — ns A15.57 0.0 — ns A15.58 — ...
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... GPIOs and Timers 3.3.16.1 General and Asynchronous Signals The MPC5200B contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency. ...
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... Figure 46. Timing Diagram—JTAG Clock Input Freescale Semiconductor Table 51. JTAG Timing Specification Characteristic ( ( Midpoint Voltage Numbers shown reference MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Min Max Unit SpecID 0 25 MHz A17.1 40 — ns A17.2 1.08 — ns A17.3 0 ...
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... TCK TDI, TMS TDO TDO Figure 49. Timing Diagram—Test Access Port Figure 47. Timing Diagram—JTAG TRST MPC5200B Data Sheet, Rev. 1 Numbers shown reference Table 51 INPUT DATA VALID OUTPUT DATA VALID Numbers shown reference Table 51 INPUT DATA VALID ...
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... Package Description 4.1 Package Parameters The MPC5200B uses TE-PBGA package. The package parameters are as provided in the following list: • Package outline • Interconnects: 272 • Pitch: 1.27 mm 4.2 Mechanical Dimensions Figure 50 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200B, 272 TE-PBGA package ...
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... D INDEX 0 TOP VIEW (D1) 19X e 19X (E1 BOTTOM VIEW Figure 50. Mechanical Dimensions and Pinout Assignments for the MPC5200B, 272 TE-PBGA 62 C 272X 0 ...
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... Pinout Listings See details in the MPC5200B User Manual [1]. Name Alias MEM_CAS CAS MEM_CLK_EN CLK_EN MEM_CS MEM_DQM[3:0] DQM MEM_MA[12:0] MA MEM_MBA[1:0] MBA MEM_MDQS[3:0] MDQS MEM_MDQ[31:0] MDQ MEM_CLK MEM_CLK MEM_RAS RAS MEM_WE EXT_AD[31:0] PCI_CBE_0 PCI_CBE_1 PCI_CBE_2 PCI_CBE_3 PCI_CLOCK PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_IRDY PCI_PAR ...
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... Package Description Table 52. MPC5200B Pinout Listing (continued) Name Alias PCI_TRDY LP_ACK LP_ALE LP_OE LP_RW LP_TS LP_CS0 LP_CS1 LP_CS2 LP_CS3 LP_CS4 LP_CS5 ATA_DACK ATA_DRQ ATA_INTRQ ATA_IOCHRDY ATA_IOR ATA_IOW ATA_ISOLATION ETH_0 TX, TX_EN ETH_1 RTS, TXD[0] ETH_2 USB_TXP, RTS, TXD[1] ETH_3 USB_PRTPWR, TXD[2] ETH_4 ...
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... Table 52. MPC5200B Pinout Listing (continued) Name Alias ETH_8 RX_DV ETH_9 CD, RX_CLK ETH_10 CTS, COL ETH_11 TX_CLK ETH_12 RXD[0] ETH_13 USB_RXD, CTS, RXD[1] ETH_14 USB_RXP, UART_RX, RXD[2] ETH_15 USB_RXN, RX, RXD[3] ETH_16 USB_OVRCNT, CTS, RX_ER ETH_17 CD, CRS PSC6_0 IRDA_RX, RxD PSC6_1 Frame, CTS ...
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... Package Description Table 52. MPC5200B Pinout Listing (continued) Name Alias I2C_3 SDA PSC1_0 TxD, Sdata_out, MOSI, TX PSC1_1 RxD, Sdata_in, MISO, TX PSC1_2 Mclk, Sync, RTS PSC1_3 BitClk, SCK, CTS PSC1_4 Frame, SS, CD PSC2_0 TxD, Sdata_out, MOSI, TX PSC2_1 RxD, Sdata_in, MISO, TX PSC2_2 Mclk, Sync, RTS ...
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... Table 52. MPC5200B Pinout Listing (continued) Name Alias TIMER_1 TIMER_2 MOSI TIMER_3 MISO TIMER_4 SS TIMER_5 SCK TIMER_6 TIMER_7 SYS_XTAL_IN SYS_XTAL_OUT RTC_XTAL_IN RTC_XTAL_OUT PORRESET HRESET SRESET IRQ0 IRQ1 IRQ2 IRQ3 SYS_PLL_TPA TEST_MODE_0 TEST_MODE_1 TEST_SEL_0 TEST_SEL_1 JTAG_TCK TCK JTAG_TDI TDI JTAG_TDO TDO JTAG_TMS TMS ...
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... All “open drain” outputs of the MPC5200B are actually regular three-state output drivers with the output data tied low and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power rail if the external signal is driven above the MPC5200B I/O power rail voltage. 5 System Design Information 5 ...
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... VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. Freescale Semiconductor Figure 51. Supply Voltage Sequencing MPC5200B Data Sheet, Rev. 1 System Design Information VDD_IO, VDD_IO_MEM (SDR) VDD_IO_MEM (DDR) ...
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... Power Supply source 5.3 Pull-up/Pull-down Resistor Requirements The MPC5200B requires external pull-up or pull-down resistors on certain pins. 5.3.1 Pull-down Resistor Requirements for TEST pins The MPC5200B requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1. 5.3.2 Pull-up Requirements for the PCI Control Lines If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification [4] ...
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... JTAG_TRST and PORRESET The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released. For more details refer to the Reset and JTAG Timing Specification. ...
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... Boards Interfacing the JTAG Port via a COP Connector The MPC5200B functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale (formerly Motorola) standard COP/BDM interface. the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order. ...
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... For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended. To reset the MPC5200B via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5200B. The circuitry shown in JTAG_TRST separately, while any other board sources can drive PORRESET ...
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... TRST 10Kohm TMS 10Kohm TCK VDD 10Kohm TDI CKSTP_OUT TDO halted NC qack Figure 54. COP Connector Diagram MPC5200B Data Sheet, Rev. 1 PORRESET MPC5200B HRESET VDD VDD SRESET VDD JTAG_TRST VDD JTAG_TMS VDD JTAG_TCK VDD JTAG_TDI TEST_SEL_0 JTAG_TDO Freescale Semiconductor ...
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... Commercial 400 -40C to 85C Industrial 266 -40C to 105C Automotive - AEC 400 -40C to 85C Automotive - AEC 400 -40C to 85C Automotive - AEC MPC5200B Data Sheet, Rev. 1 Ordering Information MPC5200B Packaging *** RoHS & pb-free RoHS & pb-free RoHS & pb-free Standard RoHS & pb-free 75 ...
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... Microprocessor Family: The Programming Environments for 32-bit Microprocessors,” Rev. 2: MPCFPE32B/ Core Reference Manual, Rev. 0: G2CORERM/D 4. “PCI Local Bus Specification,” Revision 2.2, December 18, 1998 5. “ANSI ATA-4 Specification” 6. “IEEE 802.3 Specification (ETHERNET)” 76 Table 55. Document Revision History Substantive Change(s) MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor ...
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... Freescale Semiconductor This page intentionally left blank. MPC5200B Data Sheet, Rev ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC5200BDS Rev. 1, 1/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...