MT41J64M16LA-15E Micron Semiconductor Products, MT41J64M16LA-15E Datasheet
MT41J64M16LA-15E
Available stocks
Related parts for MT41J64M16LA-15E
MT41J64M16LA-15E Summary of contents
Page 1
DDR3 SDRAM MT41J256M4 – 32 Meg Banks MT41J128M8 – 16 Meg Banks MT41J64M16 – 8 Meg Banks Features • +1.5V ±0.075V DD DD ...
Page 2
Table 2: Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Figure 1: 1Gb DDR3 Part Numbers MT41J Configuration 256 Meg x 4 128 Meg Meg x 16 Package 78-ball 9mm x 11.5mm FBGA 86-ball ...
Page 3
Table of Contents State Diagram ...
Page 4
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
List of Figures Figure 1: 1Gb DDR3 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Figure 57: Mode Register 2 (MR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 165 Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 ...
Page 8
List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
Table 52: DDR3-1600 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
State Diagram Figure 2: Simplified State Diagram Power applied Reset Power procedure on From any RESET state ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE ...
Page 11
Functional Description The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ...
Page 12
Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory internally configured as an 8-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT ZQ RESET# RZQ ZQCL, ZQCS CKE Control V Q ...
Page 13
Figure 4: 128 Meg x 8 Functional Block Diagram ODT ZQ RESET# RZQ Control CKE ZQCL, ZQCS logic A12 CK, CK# BC4 (burst chop) CS# RAS# OTF CAS# WE# Refresh 14 counter Mode registers 16 14 A[13:0] ...
Page 14
Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View Notes: 1. Ball descriptions listed in Table 3 on page 17 are ...
Page 15
Figure 7: 86-Ball FBGA – x4, x8 Ball Assignments (Top View Notes: 1. Ball descriptions listed in Table 4 on page ...
Page 16
Figure 8: 96-Ball FBGA – x16 Ball Assignments (Top View Notes: 1. Ball descriptions listed in Table 5 on page 21 are listed as ...
Page 17
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Ball Assignments Symbol K3, L7, L3, K2, A0, A1, A2, A3, L8, L2, M8, M2, A4, A5, A6, A7, N8, M3, H7, M7, A8, A9, A10/AP, K7, N3 A11, A12/BC#, A13 ...
Page 18
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (continued) Ball Assignments Symbol N2 RESET# B3, C7, DQ0, DQ1, C2, C8 DQ2, DQ3 B3, C7, C2, DQ0, DQ1, DQ2, C8, E3, E8, DQ3, DQ4, DQ5, D2, E7 DQ6, DQ7 C3, ...
Page 19
Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions Ball Assignments Symbol N3, P7, P3, N2, A0, A1, A2, A3, P8, P2, R8, R2, A4, A5, A6, A7, T8, R3, A8, A9 L7, A10/AP, R7, N7, A11, A12/BC#, T3 A13 ...
Page 20
Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions (continued) Ball Assignments Symbol T2 RESET# E3, F7, DQ0, DQ1, F2, F8 DQ2, DQ3 E3, F7, F2, DQ0, DQ1, DQ2, F8, H3, H8, DQ3, DQ4, DQ5, G2, H7 DQ6, DQ7 F3, ...
Page 21
Table 5: 96-Ball FBGA – x16 Ball Descriptions Ball Assignments Symbol N3, P7, P3, N2, A0, A1, A2, A3, P8, P2, R8, R2, A4, A5, A6, A7, T8, R3, A8, A9 L7, A10/AP, R7, N7 A11, A12/BC# M2, N8, M3 ...
Page 22
Table 5: 96-Ball FBGA – x16 Ball Descriptions (continued) Ball Assignments Symbol T2 RESET# D3 UDM E3, F7, F2, DQ0, DQ1, DQ2, F8, H3, H8, DQ3, DQ4, DQ5, G2, H7 DQ6, DQ7 D7, C3, DQ8, DQ9, C8, C2, DQ10, DQ11, ...
Page 23
Package Dimensions Figure 9: 78-Ball FBGA – x4, x8 Seating plane 1.80 ±0.25 A 0.10 A 78X ∅0.45 Dimensions apply to solder balls post-reflow. The 0.80 TYP pre-reflow diameter is 0. 0.33 NSMD ball pad. Ball A9 9.60 ...
Page 24
Figure 10: 86-Ball FBGA – x4, x8 Seating plane A 1.80 ±0.05 0.10 A CTR 86X Ø0.45 6.40 Dimensions apply to solder balls post-reflow. The pre-reflow diameter is 0. 0.33 NSMD ball pad. Ball A9 14.40 7.20 3.20 ...
Page 25
Figure 11: 96-Ball FBGA – x16 Seating plane A 1.80 ±0.05 0.10 A 96X Ø0.45 Dimensions apply 6.40 to solder balls post-reflow. The pre-reflow diameter is 0. 0.33 NSMD ball pad. Ball A9 12.00 6.00 3.20 9.00 ±0.10 ...
Page 26
Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated ...
Page 27
Thermal Characteristics Table 8: Thermal Characteristics Parameter/Condition Operating case temperature Junction-to-case (TOP) Notes: 1. MAX operating case temperature. T Figure thermal solution must be designed to ensure the DRAM device does not exceed the maxi- mum T ...
Page 28
Electrical Specifications – I The following definitions are used within the I • LOW: V • Stable: Inputs are stable at a HIGH or LOW level • Floating: Inputs are V • Switching: See Tables 10 and 11 Table 9: ...
Page 29
Table 12: Timing Parameters DDR3-800 -25E -25 I Parameter 5-5-5 6-6 (MIN RCD (MIN (MIN 52 RAS (MIN) ...
Page 30
Table 13: I Measurement Conditions for Test One Bank ACTIVATE to PRECHARGE DD Timing example CKE External clock RAS t RCD t RRD CS# HIGH between ...
Page 31
Figure 13 Example – DDR3-800, 5-5-5, x8 (-25E BA[2:0] A[9:0] 000 A10 A[12:11] 0 CS# RAS# CAS# WE# ACT Command DQ DM Notes: 1. Data DQ is shown, but ...
Page 32
Table 14: I Measurement Conditions for Power-Down Currents DD I 2Ps DD Precharge Power-Down Current 1 Name (Slow Exit) Timing example n/a CKE LOW External clock (MIN n/a t RAS n/a ...
Page 33
Figure 14: I 2N/I 3N Example – DDR3-800, 5-5-5, x8 (-25E BA[2:0] 0 A[12:0] 0000 CS# RAS# CAS# WE# Command D# D# DQ[7: PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_D2.fm - Rev C ...
Page 34
Table 15: I Measurement Conditions for Test I 4R: Burst Read Operating Current DD DD Timing diagram example CKE External clock RAS t RCD t RRD CS# HIGH ...
Page 35
Figure 15 Example – DDR3-800, 5-5- BA[2:0] 0 A[9:0] 000 A10 A[12:11] 0 CS# RAS# CAS# WE# CMD[2: DQ[7:0] DM Notes: 1. Data DQ is shown, but the output buffer should ...
Page 36
Table 16: I Measurement Conditions for 5B: Refresh DD I Test Current DD CKE HIGH External clock (MIN RAS t RCD t RRD RFC (MIN) I ...
Page 37
Table 17: I Measurement Conditions for Test I 7: All Banks Interleaved Read Current DD DD CKE HIGH External clock (MIN (MIN RAS RAS ...
Page 38
Electrical Characteristics – values are for full operating range of voltage and temperature unless otherwise DD noted. Table 19: I Maximum Limits DD Speed Bin I Width DDR3-800 x16 90 ...
Page 39
Electrical Specifications – DC and AC DC Operating Conditions Table 20: DC Electrical Characteristics and Operating Conditions All voltages are referenced to V Parameter/Condition Supply voltage I/O supply voltage Input leakage current Any input 0V ≤ V ≤ V pin ...
Page 40
Table 22: AC Input Operating Conditions Parameter/Condition Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input high AC voltage: Logic 1 Input high DC ...
Page 41
Figure 16: Input Signal Minimum V and V levels 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V ...
Page 42
Table 24: Clock, Data, Strobe, and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 42) Maximum peak amplitude allowed for undershoot area (see Figure 18 on page 42) Maximum overshoot area above V ...
Page 43
Table 25: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) All voltages are referenced to V Parameter/Condition Differential input voltage Differential input midpoint voltage Differential input voltage logic high Differential input voltage logic low Differential input crossing voltage relative ...
Page 44
Figure 20: Definition of Differential AC-Swing and V IHDIFF V IHDIFF V IHDIFF V ( ILDIFF V ILDIFF V ( ILDIFF Table 26: Allowed Time Before Ringback ( Below PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev ...
Page 45
Slew Rate Definitions for Single-Ended Input Signals Setup ( between the last crossing DS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V Hold ( between the ...
Page 46
Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev C 1/31/08 EN Electrical Specifications – DC and AC ΔTFS ΔTRH ΔTFH Micron Technology, Inc., reserves the right to change products or ...
Page 47
Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 28 and Figure 22. The nominal slew rate for a rising signal is defined ...
Page 48
ODT Characteristics ODT effective resistance R DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values are listed in Table 29 and Table 30 on page 49. A functional representation of the ODT is shown in ...
Page 49
Table 30: R Effective Impedances TT MR1 [ Resistor 120Ω 120PD240 R TT 120PU240 120Ω 60Ω 60PD120 R TT 60PU120 60Ω 40Ω R ...
Page 50
Table 31: ODT Sensitivity Definition Symbol Min R 0 × |DT Δ T(@ calibration), Δ Notes: Table 32: ODT Temperature and Voltage Sensitivity 1. Δ ...
Page 51
Table 34: Reference Settings for ODT Timing Measurements Measured Parameter AON t AOF t AONPD t AOFPD t ADC Notes: 1. Assume an RZQ of 240Ω (±1 percent) and that proper ZQ calibration has been performed at ...
Page 52
Figure 26: AONPD and AOFPD Definition t AONPD Begin point: Rising edge CK# with ODT first registered HIGH CK CK# DQ, DM DQS, DQS# TDQS, TDQS Figure 27: ADC Definition Begin ...
Page 53
Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically ...
Page 54
Table 35: 34Ω Driver Impedance Characteristics MR1[5,1] R Resistor ON 0,1 34.3Ω Ron R ON 34PU Pull-up/pull-down mismatch (MM Notes: 1. Tolerance limits assume RZQ of 240Ω (±1 percent) and are applicable after proper ZQ cali- bration has been performed ...
Page 55
Table 37: 34Ω Driver MR1[5,1] R Resistor 34.3Ω 34PD R ON 34PU Table 38: 34Ω Driver MR1[5,1] R Resistor 34.3Ω 34PD R ...
Page 56
Table 41: 34Ω Output Driver Voltage and Temperature Sensitivity Alternative 40Ω Driver Table 42: 40Ω Driver Impedance Characteristics MR1[5,1] R Resistor ON 0,0 40Ω 40PD R ON 40PU Pull-up/pull-down mismatch (MM Notes: 1. Tolerance limits assume RZQ of ...
Page 57
Table 44: 40Ω Output Driver Voltage and Temperature Sensitivity Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 45 while the differential output driver is summa- rized ...
Page 58
Table 46: Differential Output Driver Characteristics All voltages are referenced to Vss Parameter/Condition Output leakage current: DQ are disabled; 0V ≤ V ≤ ODT is disabled; ODT is HIGH OUT DD Output slew rate: Differential; For rising and ...
Page 59
Figure 30: Differential Output Signal X X Reference Output Load Figure 31 on page 59 represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output ...
Page 60
Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 45 on page 57. With the refer- ence load for timing measurements, the output slew rate for falling and rising edges is defined and measured ...
Page 61
Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 46 on page 58. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between ...
Page 62
Speed Bin Tables Table 49: DDR3-800 Speed Bins DDR3-800 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL ...
Page 63
Table 50: DDR3-1066 Speed Bins DDR3-1066 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
Page 64
Table 51: DDR3-1333 Speed Bins DDR3-1333 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
Page 65
Table 52: DDR3-1600 Speed Bins DDR3-1600 Speed Bin t t CL- RCD- RP Parameter Symbol t ACTIVATE to internal READ RCD or WRITE delay time t PRECHARGE command RP period t ACTIVATE-to-ACTIVATE or RC REFRESH command period t ACTIVATE-to-PRECHARGE RAS ...
Page 66
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C ...
Page 67
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data hold ...
Page 68
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter DQS, DQS# rising to/from rising CK, CK# DQS, DQS# rising to/from rising CK, CK# when ...
Page 69
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter DLL locking time CTRL, CMD, ADDR Base (specification) setup to CK,CK V/ns ...
Page 70
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter ZQCL command: Long POWER-UP and RESET calibration time operation Normal operation ZQCS command: Short calibration ...
Page 71
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin ...
Page 72
Table 53: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 73 Parameter R synchronous turn-on delay TT R synchronous turn-off delay TT R turn-on from ODTL on ...
Page 73
Notes 1. Parameters are applicable with 0°C 2. All voltages are referenced Output timings are only valid for R 4. Unit “ Unit “CK” represents one clock cycle of the input clock, counting the actual clock edges. ...
Page 74
The cumulative jitter error ( 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. t 18. DS (base) and 2 V/ns differential DQS, DQS# slew rate. ...
Page 75
When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for 35. The start of the write recovery time is defined as follows: – For BL8 (fixed by MRS and OTF): Rising clock edge four ...
Page 76
Command and Address Setup, Hold, and Derating The total sheet page 66) to the Δ page 77), respectively. Example: sition, the input signal has to remain above/below V (see Table 56 on page 77). Although the total setup time for ...
Page 77
Table 55: DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for Based AC175 threshold AC175 Threshold: V CMD/ ADDR 4.0 V/ns 3.0 V/ns Slew Rate Δ t Δ t Δ 1.5 59 ...
Page 78
Table 57: Minimum Required Time Below PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev C 1/31/ VAC Above for Valid Transition Slew Rate (V/ns) VAC at 175mV (ps) >2.0 ...
Page 79
Figure 34: Nominal Slew Rate and CK CK# DQS# DQS MIN MIN REF MAX ...
Page 80
Figure 35: Nominal Slew Rate for CK CK# DQS# DQS MIN MIN region REF MAX IL DC ...
Page 81
Figure 36: Tangent Line for CK CK# DQS# DQS MIN REF region MIN REF MAX ...
Page 82
Figure 37: Tangent Line for CK CK# DQS# DQS MIN MIN region REF region ...
Page 83
Data Setup, Hold, and Derating The total sheet page 66) to the Δ Example: signal has to remain above/below V page 85). Although the total setup time for slow slew rates might be negative (for example, a valid input signal ...
Page 84
Table 59: DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for Based AC175 threshold; shaded cells indicate slew rate combinations not supported 4.0 V/ns 3.0 V/ns DQ Slew Δ Δ Δ Δ Rate V/ns 2.0 ...
Page 85
Table 61: Required Time VAC Above V PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_3.fm - Rev C 1/31/ (Below VAC at 175mV (ps) Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 ...
Page 86
Figure 38: Nominal Slew Rate and CK CK# DQS# DQS MIN REF region MIN REF MAX ...
Page 87
Figure 39: Nominal Slew Rate for CK CK# DQS# DQS MIN MIN region REF MAX IL DC ...
Page 88
Figure 40: Tangent Line for CK CK# DQS# DQS MIN REF region MIN REF MAX ...
Page 89
Figure 41: Tangent Line for CK CK# DQS# DQS MIN MIN region REF region ...
Page 90
Commands Truth Tables Table 62: Truth Table – Command Notes 1–5 apply to the entire table Function Symbol MODE REGISTER SET MRS REFRESH REF Self refresh entry SRE Self refresh exit SRX Single-bank PRECHARGE PRE PRECHARGE all banks PREA Bank ...
Page 91
Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.” 6. See Table 63 for ...
Page 92
NO OPERATION (NOP) The NOP command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ CALIBRATION LONG (ZQCL) The ZQCL command is used to perform the ...
Page 93
Table 64: READ Command Summary Function Symbol READ BL8MRS, BC4MRS RD BC4OTF RDS4 BL8OTF RDS8 READ BL8MRS, BC4MRS RDAP with auto BC4OTF RDAPS4 precharge BL8OTF RDAPS8 WRITE The WRITE command is used to initiate a burst write access to an ...
Page 94
However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH ...
Page 95
SELF REFRESH The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in the self refresh mode, the DRAM retains data without external clocking. The self refresh ...
Page 96
Figure 43: DLL Enable Mode to DLL Disable Mode T0 T1 Ta0 CK# CK CKE MRS 2 SRE 3 Command NOP t MOD 6 ODT 9 Notes: 1. Any valid command. 2. Disable DLL by setting MR1[0] to “1.” 3. ...
Page 97
Figure 44: DLL Disable Mode to DLL Enable Mode T0 Ta0 Ta1 CK# CK CKE SRE 1 Command NOP NOP t CKSRE 7 ODTL off + 1 × ODT 10 Notes: 1. Enter SELF REFRESH. 2. Exit SELF ...
Page 98
Figure 45: DLL Disable DQSCK Timing T0 T1 CK# CK READ NOP Command Valid Address DQS, DQS# DLL on DQ BL8 DLL on RL (DLL disable ( DQS, DQS# DLL off DQ ...
Page 99
DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time NOM ready to operate with a new clock ...
Page 100
Write Leveling For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to ...
Page 101
When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK’s status. The prime DQ for configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The ...
Page 102
Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[ “1,” assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The ...
Page 103
Figure 48: Write Leveling Sequence CK# CK MRS 1 NOP 2 Command t MOD ODT t WLDQSEN Differential DQS 4 Prime DQ 5 Early remaining DQ Late remaining DQ Notes: 1. MRS: Load MR1 to enter write leveling mode. 2. ...
Page 104
Figure 49: Exit Write Leveling T0 T1 CK# CK Command NOP NOP Address ODT R DQS, R DQS DQS, DQS# R _DQ TT t WLO + t WLOE DQ Notes: 1. The DQ result, “= 1,” between Ta0 ...
Page 105
Operations Initialization The following sequence is required for power up and initialization, as shown in Figure 50 on page 106: 1. Apply power. RESET# is recommended to be below 0.2 × V ensure the outputs remain disabled (High-Z) and ODT ...
Page 106
Figure 50: Initialization Sequence T (MAX) = 200ms V DD See power-up conditions in the initialization sequence text, V set REF Power-up t VTD ramp CK 20ns RESET# ...
Page 107
Mode Registers Mode registers (MR0–MR3) are used to define various modes of programmable opera- tions of the DDR3 SDRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization, and it retains the stored information (except ...
Page 108
Figure 52: MRS-to-nonMRS Command Timing ( Command Address Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, must be satisfied, and no data bursts can be in progress). 2. Prior to Ta2 ...
Page 109
Figure 53: Mode Register 0 (MR0) Definitions M15 M14 Mode Register 0 0 Mode register 0 (MR0 Mode register 1 (MR1 Mode register 2 (MR2 Mode register 3 (MR3) Notes: 1. MR0[16, 13, 7, ...
Page 110
Table 68: Burst Order Starting Column Burst READ/ Address Length WRITE (A[2, 1, 0]) 4 chop READ ...
Page 111
Precharge Power-Down (Precharge PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a lower standby current mode; however, MR0[12] is set ...
Page 112
Mode Register 1 (MR1) The mode register 1 (MR1) controls additional functions and features not available in the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration only), DLL ENABLE/DLL DISABLE, R CAS ADDITIVE latency, and OUTPUT ...
Page 113
The DRAM is not tested to check—nor does Micron warrant compliance with—normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the ...
Page 114
On-Die Termination ODT resistance R termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports multiple R and RZQ is 240Ω. Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and ...
Page 115
Figure 56: READ Latency ( BC4 T0 T1 CK# CK Command ACTIVE n READ n t RCD (MIN) DQS, DQS# DQ Mode Register 2 (MR2) The mode register 2 (MR2) controls additional functions and features ...
Page 116
CAS Write Latency (CWL) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corre- sponding ...
Page 117
SRT vs. ASR If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of 95°C is needed, the user ...
Page 118
Mode Register 3 (MR3) The mode register 3 (MR3) controls additional functions and features not available in the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 59. The ...
Page 119
Figure 60: Multipurpose Register (MPR) Block Diagram Memory core Notes predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the data flow comes from the memory core or ...
Page 120
A[9:3] are a “Don’t Care” • A10 is a “Don’t Care” • A11 is a “Don’t Care” • A12: Selects burst chop mode on-the-fly, if enabled within MR0 • A13 is a “Don’t Care” • BA[2:0] are a “Don’t ...
Page 121
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 CK# CK READ 1 Command PREA MRS NOP MOD Bank address 3 Valid 0 2 A[1: ...
Page 122
Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...
Page 123
Figure 63: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...
Page 124
Figure 64: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...
Page 125
MPR Read Predefined Pattern The predetermined read calibration pattern is a fixed pattern The following is an example of using the read out predetermined read calibration pattern. The example is to ...
Page 126
DDR3 SDRAM need a longer time to calibrate R and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example ...
Page 127
ACTIVATE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. ...
Page 128
READ READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row ...
Page 129
Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 72 on page 131 (BC4 is shown in ...
Page 130
Figure 69: Consecutive READ Bursts (BL8 CK# CK Command 1 READ NOP NOP NOP t CCD Bank, Address 2 Col n DQS, DQS Notes: 1. NOP commands are shown for ease ...
Page 131
Figure 71: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS# DQ Notes ...
Page 132
Figure 73: READ (BC4) to WRITE (BC4) OTF CK# CK Command 1 READ NOP NOP NOP READ-to-WRITE command delay = CCD Bank, Address 2 Col n DQS, ...
Page 133
Figure 75: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 76: READ to PRECHARGE ( ...
Page 134
A DQS to DQ output timing is shown in Figure 78 on page 135. The DQ transitions between valid data outputs must be within DQS must also maintain a minimum HIGH and LOW time of READ preamble, the DQ balls ...
Page 135
Figure 78: Data Output Timing – DQSQ and Data Valid Window T0 T1 CK# CK Command 1 READ NOP Bank, Address 2 Col n DQS, DQS (last data valid (first data no longer valid) All ...
Page 136
HZ and parameters are referenced to a specific voltage level which specifies when the device output is no longer driving t LZ (DQ). Figure 80 shows a method to calculate the point when the device is no longer driving ...
Page 137
Figure 81: RPRE Timing CK CK# DQS Single-ended signal provided as background information DQS# Single-ended signal provided as background information DQS - DQS# Resulting differential signal relevant for t RPRE specification t Figure 82: RPST Timing DQS Single-ended signal, ...
Page 138
WRITE WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being ...
Page 139
Figure 83: WPRE Timing CK CK# DQS - DQS# Resulting differential t Figure 84: WPST Timing CK CK# DQS - DQS# Resulting differential signal relevant for t WPST specification PDF: 09005aef826aa906/Source: 09005aef82a357c3 1Gb_DDR3_4.fm - Rev C 1/31/ ...
Page 140
Figure 85: Write Burst CK# CK Command 1 WRITE NOP NOP CWL Bank, Address 2 Col n t DQSS (MIN) DQS, DQS DQSS (NOM) DQS, DQS DQSS ...
Page 141
Figure 86: Consecutive WRITE (BL8) to WRITE (BL8 CK# CK Command 1 WRITE NOP NOP NOP t CCD Address 2 Valid DQS, DQS Notes: 1. NOP commands are shown for ease ...
Page 142
Figure 88: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...
Page 143
Figure 90: WRITE to READ (BC4 Mode Register Setting CK# CK Command 1 WRITE NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of illustration; other commands may be ...
Page 144
Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF CK# CK Command 1 WRITE NOP NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of ...
Page 145
Figure 92: WRITE (BL8) to PRECHARGE CK# CK Command WRITE NOP NOP NOP Address Valid CWL DQS, DQS# DQ BL8 Notes data-in from column n. 2. Seven subsequent ...
Page 146
Figure 94: WRITE (BC4 OTF) to PRECHARGE CK# CK Command 1 WRITE NOP NOP Bank, Address 3 Col n DQS, DQS Notes: 1. NOP commands are shown for ease of illustration; other commands may be ...
Page 147
Figure 95: Data Input Timing DQS, DQS PRECHARGE Input A10 determines whether one bank or all banks are to be precharged, and in the case where only one bank precharged, inputs BA[2:0] select the bank. ...
Page 148
Before a command requiring a locked DLL can be applied, a ZQCL command must be issued, be off during Figure 96: Self Refresh Entry/Exit Timing CKSRE CPDED CKE t ...
Page 149
Extended Temperature Usage Micron’s DDR3 SDRAM support the optional extended temperature range of 0°C to 95° Thus, the SRT and ASR options must be used at a minimum. C The extended temperature range DRAM must be refreshed externally ...
Page 150
Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is ...
Page 151
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must valid state but all other input signals are a “Don’t Care.” If RESET# goes ...
Page 152
Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit Command NOP t IS CKE Enter power-down mode Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ...
Page 153
Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP Ta0 Ta1 CK# CK READ/ Command NOP NOP NOP RDAP CKE Address Valid DQS, DQS# DQ BL8 DQ BC4 Figure 101: ...
Page 154
Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP Ta0 Ta1 CK# CK WRAP NOP NOP NOP Command CKE Address Valid A10 CWL DQS, DQS# DQ BL8 DQ BC4 t Notes ...
Page 155
Figure 104: ACTIVATE to Power-Down Entry Command ACTIVE Address Valid CKE t ACTPDEN Figure 105: PRECHARGE to Power-Down Entry Command PRE All/single Address bank ...
Page 156
Figure 106: MRS Command to Power-Down Entry Command MRS NOP Address Valid CKE Figure 107: Power-Down Exit to Refresh to Power-Down Entry Command NOP ...
Page 157
RESET The RESET signal (RESET asynchronous signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, ...
Page 158
Figure 108: RESET Sequence System RESET (warm boot) Stable and valid clock CK (MIN) = MAX (10ns CK 100ns (MIN) t IOZ RESET# T=10ns (MIN) CKE ODT Command DM Address A10 BA[2:0] High-Z DQS ...
Page 159
On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ...
Page 160
Table 75: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[ ODT Pin 000 0 000 1 000–101 0 000–101 1 110 and 111 X Notes: 1. Assumes dynamic ODT is disabled (see "Dynamic ...
Page 161
Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination ...
Page 162
Table 78: Mode Registers for R MR1 ( NOM Notes: 1. RZQ = 240Ω Table 79: ...
Page 163
Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 Address Valid ODTH4 ODT ODTL DQS, DQS# DQ Notes: 1. Via MRS ...
Page 164
Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTL CNW Address Valid ODTL ON ODT R TT DQS, DQS# DQ Notes: 1. Via ...
Page 165
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 CK# CK Command NOP WRS4 NOP ODTL Address Valid ODT ODTL DQS, DQS# DQ Notes: 1. Via MRS or ...
Page 166
Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either R modes are: • Any bank active with CKE HIGH • Refresh mode with CKE HIGH • Idle mode with CKE ...
Page 167
Table 81: Synchronous ODT Parameters Symbol Description ODTL on ODT synchronous turn-on delay ODTL off ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ...
Page 168
Figure 116: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTL Notes NOM 2. ODT ...
Page 169
ODT Off During READs As the DDR3 SDRAM cannot terminate and drive at the same time least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R amble as shown in the ...
Page 170
Figure 117: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTL off = CWL + ODT DQS, DQS# DQ Notes: 1. ODT must be ...
Page 171
Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either R precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchro- nously when the DLL is synchronizing after being reset. See "Power-Down ...
Page 172
Figure 118: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Notes ignored. Table 82: Asynchronous ODT Timing Parameters for All ...
Page 173
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off ...
Page 174
Table 83: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Power-down entry transition period (power-down entry) Power-down exit transition period (power-down exit) ODT to R turn-on delay (ODTL ODT to ...
Page 175
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by ...
Page 176
Figure 120: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit Ta0 CK# CK CKE COMMAND t ANPD ODT A asynchronous t AOFPD (MIN) DRAM NOM asynchronous t AOFPD (MAX) ...
Page 177
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, ...
Page 178
Figure 121: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping CK# CK Command REF NOP NOP NOP CKE t ANPD Short CKE LOW transition period (R Notes ...
Page 179
Figure 122: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping CK# CK Command NOP NOP NOP NOP NOP ANPD Short CKE HIGH transition period (R Notes: 1. ...
Page 180
S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their ...