MT46H64M16LFCK-6 Micron Semiconductor Products, MT46H64M16LFCK-6 Datasheet

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MT46H64M16LFCK-6

Manufacturer Part Number
MT46H64M16LFCK-6
Description
Manufacturer
Micron Semiconductor Products
Datasheet

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Mobile DDR SDRAM
MT46H64M16LF – 16 Meg x 16 x 4 banks
MT46H32M32LF – 8 Meg x 32 x 4 banks
Features
• V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• Four internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
• Programmable burst lengths: 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh
Table 2:
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
1gb_ddr_mobile_sdram_t48m_density__1.fm - Rev. G 07/08 EN
Options
• V
• Configuration
Architecture
Configuration
Refresh count
Row addressing
Column addressing
architecture; two data accesses per clock cycle
aligned with data for WRITEs
per byte
rate
– 1.8V/1.8V
– 64 Meg x 16 (16 Meg x 16 x 4 banks)
– 32 Meg x 32 (8 Meg x 32 x 4 banks)
DD/
DD
/V
V
DD
DD
Q = 1.70–1.95V
Q
Configuration Addressing
Products and specifications discussed herein are subject to change by Micron without notice.
16 Meg x 16 x 4 banks
64 Meg x 16
16K (A[13:0])
1K (A[9:0])
Marking
8K
1
64M16
32M32
H
1
Options
• Row-size option
• Plastic “green” package
• Timing – cycle time
• Power
• Operating temperature range
• Revision
Notes: 1. Contact factory for availability.
Table 1:
– JEDEC-standard option
– Reduced page-size option
– 60-ball VFBGA (10mm x 11.5mm)
– 90-ball VFBGA (10mm x 13mm)
– 5ns @ CL = 3
– 5.4ns @ CL = 3
– 6ns @ CL = 3
– 7.5ns @ CL = 3
– Standard I
– Low-power I
– Commercial (0° to +70°C)
– Industrial (–40°C to +85°C)
Speed Grade
8 Meg x 32 x 4 banks
32 Meg x 32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8K (A[12:0])
1K (A[9:0])
2. Only available for x16 configuration.
3. Only available for x32 configuration.
-54
-75
-5
-6
1Gb: x16, x32 Mobile DDR SDRAM
8K
(continued)
Key Timing Parameters (CL = 3)
DD
DD
2/I
Clock Rate (MHz)
2/I
DD
DD
6
6
200
185
166
133
Reduced Page-Size Option
©2007 Micron Technology, Inc. All rights reserved.
1
8 Meg x 32 x 4 banks
32 Meg x 32
16K (A[13:0])
512 (A[8:0])
3
2
Access Time
8K
Marking
5.0ns
5.0ns
5.5ns
6.0ns
Features
None
None
CM
-54
-75
LG
CK
LF
-5
-6
IT
:A
L

Related parts for MT46H64M16LFCK-6

MT46H64M16LFCK-6 Summary of contents

Page 1

Mobile DDR SDRAM MT46H64M16LF – 16 Meg banks MT46H32M32LF – 8 Meg banks Features • 1.70–1.95V DD/ DD • Bidirectional data strobe per byte of data (DQS) • ...

Page 2

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of Figures Figure 1: 1Gb Mobile DDR Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of Tables Table 1: Key Timing Parameters ( ...

Page 5

Figure 1: 1Gb Mobile DDR Part Numbering Micron Technology Product family 46 = Mobile DDR SDRAM Operating voltage H = 1.8/1.8V Configuration 64 Meg Meg x 32 Addressing LF = Mobile standard addressing LG = Reduced page-size ...

Page 6

Functional Block Diagrams Figure 2: Functional Block Diagram (64 Meg x 16) CKE CK# CK CS# Control logic WE# CAS# Refresh RAS# counter Standard mode register Extended mode register address Address address BA0, BA1 register PDF: 09005aef82ce3074/Source: 09005aef82cd0158 1gb_ddr_mobile_sdram_t48m_density__2.fm - ...

Page 7

Figure 3: Functional Block Diagram (32 Meg x 32) CKE CK# CK Control CS# logic WE# CAS# RAS# Refresh counter Standard mode register Extended mode register address Address, Address BA0, BA1 register PDF: 09005aef82ce3074/Source: 09005aef82cd0158 1gb_ddr_mobile_sdram_t48m_density__2.fm - Rev. G 07/08 ...

Page 8

Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA Assignments – 10mm x 11.5mm (Top View Notes test pin that must be tied to V PDF: 09005aef82ce3074/Source: ...

Page 9

Figure 5: 90-Ball VFBGA Ball Assignments – 10mm x 13mm (Top View Notes test pin that must be tied to V ...

Page 10

Table 3: VFBGA Ball Descriptions 60-Ball VFBGA 90-Ball VFBGA G2 G9, G8, G7 G9, G8, G7 F2, F8 K8, K2, F8, F2 H8, H9 H8, H9 J8, J9, K7, K8, K2, J8, J9, ...

Page 11

Table 3: VFBGA Ball Descriptions (Continued) 60-Ball VFBGA 90-Ball VFBGA A7, B1, C9, D1, A7, B1, C9, D1, E9 E9, L9, M1, N9, P1, R7 A3, B9, C1, E1 A3, B9, C1, E1, L1, M9, N1, P9, R3 A9, F9, ...

Page 12

Package Dimensions Figure 6: 60-Ball VFBGA Package Seating plane 0 60X Ø0.45 10 ±0.1 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.6 7.2 0.8 TYP 0.8 ...

Page 13

Figure 7: 90-Ball VFBGA Package Seating plane A 0.1 A 90X Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 Notes: 1. All dimensions ...

Page 14

Electrical Specifications Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...

Page 15

Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued) Notes: 1–5 apply to all parameters/conditions in this table; V Parameter/Condition Operating temperature Commercial Industrial Notes: 1. All voltages referenced All parameters assume proper device initialization. 3. Tests ...

Page 16

Table 6: Capacitance (x16, x32) Note 1 applies to all the parameters in this table Parameter Input capacitance: CK, CK# Delta input capacitance: CK, CK# Input capacitance: command and address Delta input capacitance: command and address Input/output capacitance: DQs, DQS, ...

Page 17

Table 7: I Specifications and Conditions (x16) DD Notes: 1–5 apply to all the parameters/conditions in this table; notes appear on page 19 1.70–1.95V DD DD Parameter/Condition Operating one bank active-precharge current ...

Page 18

Table 8: I Specifications and Conditions (x32) DD Notes: 1–5 apply to all parameters/conditions in this table; notes appear on page 19 1.70–1.95V DD DD Parameter/Condition Operating one bank active-precharge current ...

Page 19

Table Specifications and Conditions DD Notes: 1–5, 7, and 12; apply to all the parameters/conditions in this table; V Parameter/Condition Self refresh CKE = LOW (MIN); Address and control inputs are stable; ...

Page 20

Figure 8: Typical Self Refresh Current vs. Temperature 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 -40 -35 -30 -25 -20 -15 -10 PDF: 09005aef82ce3074/Source: 09005aef82cd0158 1gb_ddr_mobile_sdram_t48m_density__2.fm - Rev. G 07/ ...

Page 21

Table 10: Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–9 apply to all the parameters in this table; V Parameter Access window of DQs from CK/CK Clock cycle time ...

Page 22

Table 10: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–9 apply to all the parameters in this table; V Parameter Address and control input setup time (fast slew rate) Address and control input setup time (slow slew rate) ...

Page 23

For the half-strength driver with a nominal 10pF load, parameters in the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use ...

Page 24

READs and WRITEs with auto precharge must not be issued until prior to the internal PRECHARGE command being issued. 22. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125µs. 23. This is not a ...

Page 25

Table 11: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions Pull-Down Current (mA) Voltage (V) Min 0.00 0.00 0.10 2.80 0.20 5.60 0.30 8.40 0.40 11.20 0.50 ...

Page 26

Table 12: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values. Characteristics are specified under best and worst process variations/conditions. Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 11.76 0.70 13.72 0.80 15.68 0.85 16.66 0.90 ...

Page 27

Table 13: Target Output Drive Characteristics (One-Half Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 10.16 0.85 10.80 0.90 10.80 0.95 ...

Page 28

Functional Description The Mobile DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the ...

Page 29

Commands Table 14 and Table 15 provide a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables (Table 16 on page 36, Table 17 on page 37, and Table 18 ...

Page 30

DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected Mobile DDR ...

Page 31

READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided on inputs A[0:Ai] (where i = the most significant column ...

Page 32

DM input logic level appearing coincident with the data given DM signal is regis- tered LOW, the corresponding data will be written to memory; if the DM signal is regis- tered HIGH, the corresponding data inputs will be ...

Page 33

PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( whether one or all ...

Page 34

AUTO REFRESH AUTO REFRESH is used during normal operation of the Mobile DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. ...

Page 35

DEEP POWER-DOWN The DEEP POWER-DOWN (DPD) command is used to enter DPD operating mode, which achieves maximum power reduction by eliminating the power of the memory array. Data will not be retained when the device enters DPD mode. The DPD ...

Page 36

Operations Table 16: Truth Table – Current State Bank n – Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle ...

Page 37

The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not shown ...

Page 38

Notes: 1. This table applies when CKE the previous state was self refresh), after down full initialization if the previous state was deep power-down). 2. This table describes alternate bank operation, except where noted (for example, the cur- ...

Page 39

Table 18: Truth Table – CKE Notes: 1–4 CKE CKE Current State Active power-down L L Deep power-down L L (Precharge) power-down L L Self refresh L H Active power-down L H Deep power-down ...

Page 40

Figure 14: Mobile DRAM Simplified State Diagram Power Power on applied PRE PREALL LMR LMR EMR WRITE WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD ...

Page 41

Initialization The following sections provide detailed information covering device initialization, register definition, and device operation. Prior to normal operation, Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Initialization procedures, other than those specified, will result ...

Page 42

Figure 15: Initialize and Load Mode Registers ( ( ) ) CK LVCMOS HIGH LEVEL ( ( ) ) CKE ( ( ...

Page 43

Register Definition Mode Registers The mode registers are used to define the specific mode of operation of the Mobile DDR SDRAM. Two mode registers are used to specify the operational characteristics of the device: standard mode register and extended mode ...

Page 44

Burst Length (BL) Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length (BL) being programmable. The BL determines the maximum number of column locations that can be accessed for a given READ or ...

Page 45

Table 19: Burst Definition Table Burst Length Starting Column Address ...

Page 46

CAS Latency (CL) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first output data. The latency can be set clocks, as shown in ...

Page 47

The extended mode register is programmed via the LOAD MODE REGISTER command with BA0 = 0 and BA1 = 1. Information in the extended mode register will be retained until it is programmed again, the device goes into deep power-down ...

Page 48

Figure 18: Extended Mode Register BA1 n Mode Register Definition 0 0 Standard mode register 0 1 Status register 1 0 Extended mode register 1 1 Reserved En ... E10 ...

Page 49

Figure 19: SRR Timing T0 T1 CK# CK Command 1 PRE NOP t RP Address BA0, BA1 DQS DQ Notes: 1. All banks must be idle prior to status register read. 2. NOP or DESELECT commands are required between LMR ...

Page 50

Figure 20: Status Register Definition DQ31..DQ16 DQ15 DQ14 DQ13 S31..S16 S15 S14 S13 31.. Reserved Density S15 S14 S13 Density 128Mb 256Mb 512Mb 1Gb ...

Page 51

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by ...

Page 52

Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 26 on page 57. A READ burst ...

Page 53

Figure 22: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if 4, ...

Page 54

Figure 23: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if burst ...

Page 55

Figure 24: Random READ Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if ...

Page 56

Figure 25: Terminating a READ Burst T0 CK# CK Command READ Banka, Address Col n DQS DQ T0 CK# CK Command READ Banka, Address Col n DQS DQ Notes: 1. Dout n = data-out from column ...

Page 57

Figure 26: READ-to-WRITE T0 CK# CK Command READ Bank, Address Col n DQS CK# CK Command READ Bank, Address Col n DQS DQ DM Notes OUT the ...

Page 58

Figure 27: READ-to-PRECHARGE T0 CK# CK Command READ Banka, Address Col n DQS DQ T0 CK# CK Command READ Banka, Address Col n DQS DQ Notes OUT interrupted burst ...

Page 59

Figure 28: Data Output Timing – CK LDQS DQ (Last data valid (First data no longer valid (Last data valid ...

Page 60

DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition derived from the ...

Page 61

Figure 30: Data Output Timing – T0 CK# CK Command READ 1 DQS or LDQS/UDQS 2 All DQ values, collectively Notes transitioning after DQS transitions define 2. All DQ must transition the DQ ...

Page 62

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 11 on page 32. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...

Page 63

Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 41 on page 72 and Figure 42 on page 73. Note that only the data-in pairs that are registered prior to the subsequent ...

Page 64

Figure 32: Write – DM Operation CKE Command NOP ACTIVE Row Address A10 Row BA0, BA1 Bank ...

Page 65

Figure 33: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes uninterrupted burst shown. 3. A10 is LOW with the WRITE command (auto precharge is disabled). PDF: ...

Page 66

Figure 34: Consecutive WRITE-to-WRITE T0 CK# CK Command WRITE Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes uninterrupted burst shown. 3. Each WRITE command may be to any bank. ...

Page 67

Figure 36: Random WRITE Cycles T0 CK# CK Command WRITE Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes ( the next data-in following D burst order. 3. ...

Page 68

Figure 37: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS ...

Page 69

Figure 38: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS ...

Page 70

Figure 39: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS ...

Page 71

Figure 40: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS ...

Page 72

Figure 41: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS ...

Page 73

Figure 42: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS t DQSS (NOM) DQS DQSS t DQSS (MIN) DQS DQSS ...

Page 74

Care.” After a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there ...

Page 75

Figure 43: Bank Read – with Auto Precharge CKE Command ACTIVE NOP Address Row A10 Row ...

Page 76

Figure 44: Bank Read – Without Auto Precharge CKE Command 6 ACTIVE NOP Row Address A10 Row BA0, ...

Page 77

Figure 45: Bank Write – with Auto Precharge CKE Command ACTIVE NOP Address Row A10 Row ...

Page 78

Figure 46: Bank Write – Without Auto Precharge CKE Command ACTIVE NOP Address Row A10 Row ...

Page 79

Auto Refresh Auto refresh mode is used during normal operation of the Mobile DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is ...

Page 80

Self Refresh The self refresh mode can be used to retain data in the Mobile DDR SDRAM even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without ...

Page 81

Power-Down Power-down (Figure 49 on page 81) is entered when CKE is registered LOW. If power- down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active ...

Page 82

Figure 50: Power-Down Mode (Active or Precharge CKE Command 1 Valid Address Valid DQS READ/WRITE access in progress power-down Notes: ...

Page 83

Figure 51: Deep Power-Down T0 CK# CK CKE Command NOP All banks idle with no activity on the data bus Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = deep power-down. 3. Upon exit of ...

Page 84

Figure 52: Clock Stop Mode CK CKE ( ( ) ) Command ( ( ) ) ( ( ) ) Address ( ( ) ) ( ( ...

Page 85

Revision History: Device Rev ...

Page 86

Table 10, “Electrical Characteristics and Recommended AC Operating Conditions,” on page 21: Changed Rev ...

Page 87

Revision History: Commands, Operations, and Timing Diagrams Revision History: Commands, Operations, and Timing Diagrams Update . . . . . . . . . . . . . . . . . . . . . . . . . ...

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