MT47H128M16HG-3 Micron Semiconductor Products, MT47H128M16HG-3 Datasheet
MT47H128M16HG-3
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MT47H128M16HG-3 Summary of contents
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DDR2 SDRAM MT47H512M4 – 64 Meg banks MT47H256M8 – 32 Meg banks MT47H128M16 – 16 Meg banks For the latest data sheet, refer to Micron’s Web site: Features ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 2Gb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 61: ODT Timing for Slow-Exit or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Part Numbers Figure 1: 2Gb DDR2 Part Numbers MT47H Configuration Note: Not all speeds and configurations are available. Contact Micron sales for current revision. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that ...
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The 2Gb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at ...
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Ball Assignment and Description Figure 2: 84-Ball FBGA (x16) 11.5mm x 14mm (top view PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev ...
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Figure 3: 60-Ball FBGA (x4, x8) 11.5mm x 14mm (top view PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev NF, RDQS#/NU ...
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Table 3: 84-/60-Ball Descriptions x16 Ball x4, x8 Ball Number Number Symbol K9 F9 J8, K8 E8, F8 CK, CK K7, L7, F7, G7, RAS#, CAS F3, B3 LDM, UDM B3 L2, L3, L1 ...
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Table 3: 84-/60-Ball Descriptions x16 Ball x4, x8 Ball Number Number Symbol G8, G2, H7, – DQ0–DQ3, H3, DQ4–DQ7, H1, H9, F1, F9, DQ8–DQ10, C8, C2, D7, D3, D1, D9, B1, B9 – C8, C2, D7, DQ0–DQ3 D3, D1, D9, ...
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Table 3: 84-/60-Ball Descriptions x16 Ball x4, x8 Ball Number Number Symbol – A2, A8 – B1 PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 EN (Continued) Type Description NU – Not used: Not ...
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Functional Description The 2Gb DDR2 SDRAM is a high-speed CMOS dynamic random access memory containing 2,147,483,648 bits. The 2Gb DDR2 SDRAM is internally configured bank DRAM. The 2Gb DDR2 SDRAM uses a double data rate architecture to ...
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Figure 5: Functional Block Diagram – 256 Meg x 8 ODT CKE CONTROL CK LOGIC CK# CS# RAS# CAS# WE# REFRESH MODE ROW- COUNTER REGISTERS ADDRESS 18 MUX 15 2 A0-A14, ADDRESS 18 BA0-BA2 REGISTER 3 10 Figure 6: Functional ...
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State Diagram Figure 7 shows a simplified state diagram to provide the basic command flow not comprehensive and does not identify all timing requirements or possible command restrictions. Figure 7: Simplified State Diagram OCD calibration Setting (E)MRS MRS ...
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Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 8 illustrates the sequence required for power-up and initialization. Figure 8: DDR2 Power-up and Initialization ...
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Notes: 1. Applying power; if CKE is maintained below 0 tee R ODT ball (all other inputs may be undefined; I/Os and outputs must be less than V ing voltage ramp time to avoid DDR2 SDRAM device latch-up). ...
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Issue a LOAD MODE command with LOW initialize device operation (i.e., to pro- gram operating parameters without resetting the DLL). To access the mode registers, BA0 = 0, BA1 = 0, BA2 = 0. 14. Issue ...
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Mode Register (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, oper- ating mode, DLL RESET, write recovery, and ...
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Figure 9: Mode Register (MR) Definition BA2 BA1 M17 M16 Notes: 1. A14 is not used in x16 configuration. 2. Not all listed CL options are supported in any individual speed grade. Burst ...
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Table 4: Burst Definition Burst Length Operating Mode The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 9 on page ...
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Power-Down Mode Active power-down (PD) mode is defined by bit M12, as shown in Figure 9 on page 21. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 ...
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Figure 10: CAS Latency (CL CK# CK READ NOP COMMAND DQS, DQS CK# CK READ NOP COMMAND DQS, DQS# DQ Notes Posted CAS# additive latency (AL Shown ...
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Figure 11: Extended Mode Register Definition BA2 17 16 MRS E17 E16 Notes: 1. During initialization, all three bits must be set to “1” for OCD default state, then must be set ...
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Output Drive Strength The output drive strength is defined by bit E1, as shown in Figure 11 on page 25. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit selects normal (full ...
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ODT ball will determine the R the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See “ODT Timing” on page 74 for ODT timing diagrams. Off-Chip Driver (OCD) ...
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Figure 13: WRITE Latency T0 T1 CK# CK COMMAND ACTIVE n WRITE n t RCD (MIN) DQS, DQS# DQ Notes ...
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Extended Mode Register 3 The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 15 on page 29. The EMR3 is programmed via the ...
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Command Truth Tables The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes and bank-to-bank commands. Table 5: Truth Table – DDR2 Commands Notes and 6 apply to all CKE Previous Function ...
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Table 6: Truth Table – Current State Bank n – Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS Any L H Idle ...
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The following states must not be interrupted by any executable command (DESELECT or NOP commands must be applied on each positive clock edge during these states): 6. All states and sequences not shown are illegal or reserved. 7. Not ...
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Table 7: Truth Table – Current State Bank n – Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle L L Row Activating, Active, ...
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Table 8: Minimum Delay with Auto Precharge Enabled From Command (Bank n) WRITE with auto precharge READ with auto precharge 4. REFRESH and LM commands may only be issued when all banks are idle. 5. Not used. 6. All states ...
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DESELECT, NOP, and LM Commands DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as ...
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A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by ...
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READ Command The READ command is used to initiate a burst read access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where for x16, A9 ...
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Figure 18: READ Command AUTO PRECHARGE BANK ADDRESS Figure 19: Example: Meeting T0 T1 CK# CK COMMAND ACT NOP Row ADDRESS BA0, BA1, BA2 Bank x t RRD PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 EN CK# CK CKE ...
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Figure 20: READ Latency COMMAND ADDRESS DQS, DQS# COMMAND ADDRESS DQS, DQS# COMMAND ADDRESS DQS, DQS# Notes data-out from column Three subsequent elements of data-out appear in the programmed order ...
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Figure 21: Consecutive READ Bursts CK# COMMAND ADDRESS DQS, DQS# DQ CK# COMMAND COMMAND ADDRESS ADDRESS DQS, DQS# DQ Notes ( data-out from column n (or column b Three subsequent ...
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Figure 22: Nonconsecutive READ Bursts CK# CK COMMAND ADDRESS DQS, DQS# DQ CK# CK COMMAND COMMAND ADDRESS ADDRESS DQS, DQS# DQ Notes ( data-out from column n (or column b ...
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Table 9: READ Using Concurrent Auto Precharge From Command (Bank n) READ with READ or READ with auto precharge auto WRITE or WRITE with auto precharge precharge PRECHARGE or ACTIVE Data from any READ burst must be completed before a ...
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Figure 24: READ-to-PRECHARGE – CK# CK COMMAND ADDRESS A10 DQS, DQS# DQ Notes ( 3 RTP ≥ 2 clocks Shown with nominal Figure ...
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Figure 27: Bank Read – without Auto Precharge CKE COMMAND 5 NOP 6 ACT ADDRESS 5 RA A10 5 RA BA0, BA1, BA2 Bank x t RCD t RAS 7 DM Case 1: t ...
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Figure 28: Bank Read – with Auto Precharge CKE COMMAND 5 NOP 5 ACT ADDRESS RA A10 RA BA0, BA1, BA2 Bank x t RCD t RAS DM Case (MIN) and ...
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Figure 29: x4, x8 Data Output Timing – DQ (First data no longer valid) DQ (First data no longer valid) All DQs and DQS, collectively Notes transitioning after DQS transition define T2n are “early DQS,” are ...
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Figure 30: x16 Data Output Timing – CK# CK LDSQ# LDQS 1 DQ (Last data valid (First data no longer valid (Last data valid) ...
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Figure 31: Data Output Timing – CK# CK DQS#/DQS, or LDQS#/LDQS / UDQ#/UDQS 2 DQ (Last data valid) DQ (First data valid) All DQs, collectively 3 t Notes: 1. DQSCK is the DQS output window relative to CK ...
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WRITE Command The WRITE command is used to initiate a burst write access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where for x8 and ...
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During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between ...
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Figure 33: WRITE Burst COMMAND ADDRESS t DQSS (NOM) DQS, DQS# t DQSS (MIN) DQS, DQS# t DQSS (MAX) DQS, DQS# Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the ...
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Figure 34: Consecutive WRITE-to-WRITE COMMAND ADDRESS t DQSS (NOM) DQS, DQS# Notes etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent ...
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Figure 36: Random WRITE Cycles COMMAND ADDRESS t DQSS (NOM) DQS, DQS# Notes etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following Three ...
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Figure 38: WRITE-to-READ T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col b t DQSS (NOM) WL ± t DQSS DQS, DQS DQSS (MIN DQSS DQS, DQS ...
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Figure 39: WRITE-to-PRECHARGE T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col b t DQSS (NOM DQSS DQS# DQS DQSS (MIN DQSS DQS# DQS DQSS (MAX) ...
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Figure 40: Bank Write – without Auto Precharge CKE COMMAND 5 NOP 6 ACT RA ADDRESS A10 RA BA0, BA1, BA2 Bank x t RCD DQS, DQS Notes ...
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Figure 41: Bank Write – with Auto Precharge CKE 4 COMMAND NOP 5 ACT RA ADDRESS A10 RA BA0, BA1, BA2 Bank x DQS,DQS Notes data-in from ...
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Figure 42: WRITE – DM Operation CK CKE 5 COMMAND NOP 6 ACT NOP 6 ADDRESS RA A10 RA BA0, BA1, BA2 Bank x t RCD t RAS DQS, DQS# ...
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Figure 43: Data Input Timing CK# CK DQS DQS Notes: 1. DSH (MIN) generally occurs during t 2. DSS (MIN) generally occurs during 3. WRITE command issued at T0. 4. For x16, LDQS controls the lower byte ...
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PRECHARGE Command The PRECHARGE command, illustrated in Figure 44, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time ...
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SELF REFRESH Command The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external ...
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Figure 45: Self Refresh CKE 1 COMMAND 5 NOP REF ODT 8 t AOFD / t AOFPD 8 ADDRESS DQS#, DQS Enter self refresh mode (synchronous) ...
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REFRESH Command REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-Before-RAS# (CBR) REFRESH. This command is nonpersistent must be issued each time a refresh is required. The addressing is generated by the ...
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Power-Down Mode DDR2 SDRAMs support multiple power-down modes that allow significant power savings over normal operating modes. CKE is used to enter and exit different power- down modes. Power-down entry and exit timings are shown in Figure 47 on page ...
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Figure 47: Power-Down VALID 1 COMMAND NOP CKE ADDRESS VALID DQS, DQS Enter power-down mode 2 Notes this command is a PRECHARGE (or if the device is already in the ...
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Table 11: CKE Truth Table Notes 1–3, 12 Current State Power-down Self refresh Bank(s) active All banks idle Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at ...
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Figure 48: READ to Power-Down or Self Refresh Entry T0 T1 CK# CK READ NOP COMMAND CKE VALID ADDRESS A10 DQS, DQS Notes: 1. Power-down or self refresh entry may occur after the READ burst completes. ...
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Figure 50: WRITE to Power-Down or Self-Refresh Entry T0 T1 CK# CK COMMAND WRITE NOP CKE ADDRESS VALID A10 DQS, DQS Notes: 1. Power-down or self refresh entry may occur after the WRITE burst completes. Figure ...
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Figure 52: REFRESH Command to Power-Down Entry COMMAND Notes: 1. The earliest precharge power-down entry may occur which REFRESH command. Precharge power-down entry occurs prior to Figure 53: ACTIVE Command to Power-Down Entry COMMAND ...
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Figure 54: PRECHARGE Command to Power-Down Entry CK# COMMAND ADDRESS A10 CKE Notes: 1. The earliest precharge power-down entry may occur is at T2, which CHARGE command. Precharge power-down entry occurs prior to Figure 55: LOAD MODE ...
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Precharge Power-Down Clock Frequency Change When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must logic LOW level. A minimum of two differential clock cycles must pass after CKE goes ...
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RESET Function (CKE LOW Anytime) DDR2 SDRAM applications may go into a reset state anytime during normal operation application enters a reset condition, CKE is used to ensure the DDR2 SDRAM device resumes normal operation after re-initializing. All ...
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Figure 57: RESET Function T0 T1 CK# CK CKE ODT COMMAND 2 NOP 1 READ DM 3 Col n ADDRESS A10 BA0, BA1, BA2 Bank a High-Z DQS 3 High Notes: 1. Either NOP or DESELECT ...
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ODT Timing Once a 12ns delay ( enabled via the EMR LOAD MODE command, ODT can be accessed under two timing categories. ODT will operate in either synchronous mode or asynchronous mode, depending on the state of CKE. ODT can ...
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Figure 58: ODT Timing for Entering and Exiting Power-Down Mode Synchronous st 1 CKE Any mode except self refresh mode Applicable modes t t AOND/ AOFD Applicable timing parameters MRS Command to ODT Update Delay During normal operation, the value ...
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Figure 60: ODT Timing for Active or Fast-Exit Power-Down Mode CK# CK CMD ADDR CKE ODT R TT Table 12: DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes Parameter ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ...
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Figure 61: ODT Timing for Slow-Exit or Precharge Power-Down Modes CK# CK CMD ADDR CKE ODT R TT Table 13: DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes Parameter ODT turn-on (power-down mode) ODT turn-off (power-down mode) PDF: 09005aef824f87b6/Source: ...
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Figure 62: ODT Turn-off Timings When Entering Power-Down Mode CK# CK CKE ODT R TT ODT R TT Table 14: DDR2-400/533 ODT Turn-Off Timings when Entering Power-Down Mode Parameter ODT turn-off delay ODT turn-off ODT turn-off (power-down mode) ODT to ...
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Figure 63: ODT Turn-On Timing when Entering Power-Down Mode CK# CK CKE ODT R TT ODT R TT Table 15: DDR2-400/533 ODT Turn-on Timing When Entering Power-Down Mode Parameter ODT turn-on delay ODT turn-on ODT turn-on (power-down mode) ODT to ...
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Figure 64: ODT Turn-Off Timing When Exiting Power-Down Mode CK# CK COMMAND NOP NOP NOP CKE t CKE (MIN) ODT RTT ODT RTT Table 16: DDR2-400/533 ODT Turn-off Timing When Exiting Power-Down Mode Parameter ODT turn-off delay ...
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Figure 65: ODT Turn-on Timing When Exiting Power-Down Mode T0 T1 CK# CK COMMAND NOP NOP NOP CKE t CKE (MIN) ODT RTT ODT R TT Table 17: DDR2-400/533 ODT Turn-On Timing When Exiting Power-Down Mode Parameter ODT turn-on delay ...
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Absolute Maximum Ratings Stresses greater than those listed in Table 18 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in ...
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Table 19: Temperature Limits Parameter Storage temperature Operating temperature – commercial Operating temperature – industrial Notes: 1. MAX storage case temperature; T Figure 66. This case temperature limit is allowed to be exceeded briefly during package reflow, as noted in ...
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AC and DC Operating Conditions Table 21: Recommended DC Operating Conditions (SSTL_18) All voltages referenced to V Parameter Supply voltage V L supply voltage DD I/O supply voltage I/O reference voltage I/O termination voltage (system) Notes ...
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Input Electrical Characteristics and Operating Conditions Table 23: Input DC Logic Levels All voltages referenced to V Parameter Input high (logic 1) voltage Input low (logic 0) voltage Table 24: Input AC Logic Levels All voltages referenced to V Parameter ...
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Table 25: Differential Input Logic Levels All voltages referenced to V Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross-point voltage Input midpoint voltage Notes CK#, DQS, DQS#, LDQS, LDQS#, ...
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Table 26: AC Input Test Conditions Parameter Input setup timing measurement reference level BA2–BA0, A0–A14 , A0–A13 (x16), CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE Input hold timing measurement reference level BA2–BA0, A0–A14 , A0–A13 (x16), CS#, ...
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Input Slew Rate Derating For all input signals, the total by adding the data sheet value, respectively. Example: t IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of V ...
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Table 27: DDR2-400/533 Setup and Hold Time Derating Values ( Command/ 2.0 V/ns Address Slew Δ t Rate (V/ns) IS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 –11 0.8 –25 0.7 –43 ...
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Figure 69: Nominal Slew Rate for Setup slew rate falling signal PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev ...
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Figure 70: Tangent Line for MIN MIN REF MAX MAX IL AC PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 ...
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Figure 71: Nominal Slew Rate for MIN MIN REF MAX MAX IL AC PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A ...
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Figure 72: Tangent Line for MIN MIN REF MAX MAX IL AC Hold slew rate rising signal PDF: 09005aef824f87b6/Source: 09005aef824f1182 ...
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Table 29: DDR2-400/533 DS, Notes: 1–7; all units 4.0 V/ns 3.0 V/ns Slew Δ t Δ t Δ t Δ t Rate (V/ns 2.0 125 45 125 45 ...
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Table 30: DDR2-667 DS, DH Derating Values with Differential Strobe Notes: 1–7; all units 2.8 V/ns 2.4 V/ns Slew Δ t Δ t Δ t Δ t Rate (V/ns ...
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Table 31: Single-Ended DQS Slew Rate Derating Values Using Reference points indicated in bold DQ 2.0 V/ns 1.8 V/ 130 53 130 53 130 1 ...
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Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS Reference points indicated in bold DQ 2.0 V/ns 1.8 V/ 355 341 355 341 355 1.5 ...
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Figure 73: Nominal Slew Rate for DQS DQS MIN MIN REF MAX MAX IL AC Notes: 1. DQS, DQS# signals ...
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Figure 74: Tangent Line for DQS DQS MIN MIN REF MAX MAX IL AC Setup Slew Rate Falling Signal Notes: ...
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Figure 75: Nominal Slew Rate for DQS DQS MIN MIN REF MAX MAX IL AC Notes: 1. DQS, DQS# signals ...
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Figure 76: Tangent Line for DQS DQS MIN MIN REF MAX MAX IL AC Notes: 1. DQS, DQS# signals must ...
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Figure 77: AC Input Test Signal Waveform Command/Address Balls Logic Levels V Levels REF Figure 78: AC Input Test Signal Waveform for Data with DQS, DQS# (differential) Logic Levels V Levels REF PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 ...
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Figure 79: AC Input Test Signal Waveform for Data with DQS (single-ended) Logic Levels V V Levels Levels REF REF Figure 80: AC Input Test Signal Waveform (differential PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 ...
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Power and Ground Clamp Characteristics Power and ground clamps are provided on the following input-only balls: BA2–BA0, A0– A13 ( x4, x8), A0–A12 (x16), CS#, RAS#, CAS#, WE#, ODT, and CKE. Table 35: Input Clamp Characteristics Voltage Across Clamp Figure ...
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AC Overshoot/Undershoot Specification Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V maximum average amplitude that is shown in Table 36 and Table 37. Table 36: Address and Control Balls Applies to BA2–BA0, A0–A13 ( x4, ...
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Output Electrical Characteristics and Operating Conditions Table 38: Differential AC Output Parameters Parameter AC differential cross-point voltage AC differential voltage swing Notes: 1. The typical value of V and V differential output signals must cross. Figure 84: Differential Output Signal ...
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Table 39: Output DC Current Drive Parameter Output minimum source DC current Output minimum sink DC current Notes: 1. For For I between 0V and 280mV. 3. The DC value The values of ...
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Full Strength Pull-Down Driver Characteristics Figure 86: Full Strength Pull-Down Characteristics 120.00 100.00 Table 41: Full Strength Pull-Down Current (mA) Voltage (V) PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 EN Full Strength Pull-Down Driver Characteristics Pull-down Characteristics 80.00 60.00 ...
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Full Strength Pull-Up Driver Characteristics Figure 87: Full Strength Pull-Up Characteristics -100.0 -120.0 Table 42: Full Strength Pull-Up Current (mA) PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 EN Full Strength Pull-Up Driver Characteristics Pull-up Characteristics 0.0 0.0 0.5 -20.0 ...
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Reduced Strength Pull-Down Driver Characteristics Figure 88: Reduced Strength Pull-Down Characteristics 70.00 60.00 50.00 40.00 30.00 20.00 10.00 Table 43: Reduced Strength Pull-Down Current (mA) Voltage (V) PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 EN Reduced Strength Pull-Down Driver ...
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Reduced Strength Pull-Up Driver Characteristics Figure 89: Reduced Strength Pull-Up Characteristics -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 Table 44: Reduced Strength Pull-Up Current (mA) Voltage (V) PDF: 09005aef824f87b6/Source: 09005aef824f1182 2gb_ddr2.fm - Rev. A 9/06 EN Reduced Strength Pull-Up Driver ...
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FBGA Package Capacitance Table 45: Input Capacitance Parameter Input capacitance: CK, CK# Input capacitance: BA2–BA0, A0–A14 (A0–A13 on x16), CS#, RAS#, CAS#, WE#, CKE, ODT Input/Output capacitance: DQs, DQS, DM, NF Notes: 1. This parameter is sampled ...
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I Specifications and Conditions DD Table 46: DDR2 I Specifications and Conditions (continued) DD Notes: 1–7; notes appear on page 114 Parameter/Condition Operating one bank active-precharge current RAS = ...
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Table 46: DDR2 I Specifications and Conditions (continued) DD Notes: 1–7; notes appear on page 114 Parameter/Condition Operating bank interleave read current: All bank interleaving reads 0mA OUT ...
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Table 47: General I Parameters DD I Parameter RCD ( RRD ( x4/x8 (1KB RRD ( x16 (2KB ...
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AC Operating Specifications Table 49: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet Notes: 1–5; notes appear on page 122 Characteristics Parameter Sym t CK (5) Clock cycle AVG ...
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Table 49: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet Notes: 1–5; notes appear on page 122 Characteristics Parameter Sym t QHS DQ hold skew factor output access time ...
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Table 49: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet Notes: 1–5; notes appear on page 122 Characteristics Parameter Sym t DQSH DQS input-high pulse width t DQSL DQS input-low pulse width ...
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Table 49: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet Notes: 1–5; notes appear on page 122 Characteristics Parameter Sym t IPW Address and control input pulse width for each input t ...
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Table 49: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet Notes: 1–5; notes appear on page 122 Characteristics Parameter Sym t DELAY CKE LOW to CK, CK# uncertainty t RFC REFRESH-to-ACTIVE or ...
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Table 49: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet Notes: 1–5; notes appear on page 122 Characteristics Parameter Sym t XARD Exit active power- down to READ command, MR[12 ...
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Notes 1. All voltages are referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is disabled for all measurements ...
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The intent of the “Don’t Care” state after completion of the postamble is that the DQS- driven signal should either be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input ...
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DELAY is calculated from prior to CK, CK# being removed in a system RESET condition. See “Reset Function” on page 72. t 27. ISXR is equal to Figure 45 on page 62. 28. No more than four bank-ACTIVE ...
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The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The following ...
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Package Dimensions Figure 90: 84-Ball FBGA Package – 11.5mm x 14mm (x16) SEATING PLANE 1.80 ±0.05 A 0.10 A 84X Ø0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE- REFLOW DIAMETER IS 0. 0.33 BALL A9 NSMD ...
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Figure 91: 60-Ball FBGA Package – 11.5mm x 14mm (x4/x8) SEATING PLANE A 1.80 ±0.05 CTR 0.10 A 60X Ø0.45 6.40 SOLDER BALL 0.80 DIAMETER REFERS TYP TO POST-REFLOW CONDITION. BALL A9 8.00 4.00 3.20 11.50 ±0.10 Note: All dimensions ...