MT48LC16M16A2TG Micron Semiconductor Products, MT48LC16M16A2TG Datasheet
MT48LC16M16A2TG
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MT48LC16M16A2TG Summary of contents
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... Off-center parting line. 3. Consult Micron for availability. 4. Not available in x16 configuration. 5. Actual FBGA part marking shown on page 58. Part Number Example: MT48LC16M16A2TG-75 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. MT48LC64M4A2 – 16 Meg x 4 MT48LC32M8A2 – ...
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Meg x 4 SDRAM 8mm x 16mm “FB” Vss NC B VssQ NC C DQ3 VssQ DQ2 ...
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Meg x 16 SDRAM 8mm x 14mm “FG” Vss DQ15 DQ13 V Q DQ14 DD C DQ11 V Q DQ12 SS D DQ9 V Q DQ10 DD E NC/SV ...
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... PART NUMBER ARCHITECTURE MT48LC64M4A2TG 64 Meg x 4 MT48LC64M4A2FB* 64 Meg x 4 MT48LC32M8A2TG 32 Meg x 8 MT48LC32M8A2FB* 32 Meg x 8 MT48LC16M16A2TG 16 Meg x 16 MT48LC16M16A2FG 16 Meg x 16 *Actual FBGA part marking shown on page 58. GENERAL DESCRIPTION The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory 268,435,456 bits internally configured as a quad- ...
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TABLE OF CONTENTS Functional Block Diagram – 64 Meg x 4 .................... Functional Block Diagram – 32 Meg x 8 .................... Functional Block Diagram – 16 Meg x 16 .................. Pin Descriptions .......................................................... 10 Ball Descriptions .......................................................... 10 Functional Description ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 11 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 FUNCTIONAL BLOCK DIAGRAM 64 Meg x 4 SDRAM ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 10 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 FUNCTIONAL BLOCK DIAGRAM 32 Meg x 8 SDRAM ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 9 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 FUNCTIONAL BLOCK DIAGRAM 16 Meg x 16 SDRAM ...
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PIN DESCRIPTIONS 54-PIN TSOP SYMBOL 38 CLK 37 CKE 19 CS# 16, 17, 18 WE#, CAS#, RAS# 39 x4, x8: DQM 15, 39 x16: DQML 20, 21 BA0, BA1 23-26, 29-34, 22, 35, 36 A0-A12 2, ...
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BALL DESCRIPTIONS 54-BALL FBGA SYMBOL F2 CLK F3 CKE G9 CS# F7, F8, F9 CAS#, RAS#, WE# E8, F1 LDQM, UDQM G7, G8 BA0, BA1 H7, H8, J8, J7, J3, J2, A0–A12 H3, H2, H1, G1, G3, H9, G2, A8, ...
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BALL DESCRIPTIONS 60-BALL FBGA SYMBOL K2 CLK L2 CKE L8 CS# J8, K7, J7 CAS#, RAS#, WE# J2 DQM, M8, M7 BA0, BA1 N7, P8, P7, R8, R1, P2, P1, A0–A12 N2, N1, M2, N8, M1, L1 C7, F7, F2, ...
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FUNCTIONAL DESCRIPTION In general, the 256Mb SDRAMs (16 Meg banks, 8 Meg banks and 4 Meg banks) are quad- bank DRAMs that operate at 3.3V and include a ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is deter- mined ...
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CAS Latency The CAS latency is the delay, in clock cycles, be- tween the registration of a READ command and the availability of the first piece of output data. The la- tency can be set to two or three clocks. ...
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Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written de- scription of each command. Three additional TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) NO ...
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, re- gardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The ...
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BURST TERMINATE The BURST TERMINATE command is used to trun- cate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of ...
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Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be is- sued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the AC- TIVE command, which selects both the bank ...
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READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are pro- vided with the READ command, and auto precharge is either enabled or disabled for that burst access. If ...
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This is shown in Figure 7 for CAS latencies of two and three; data element either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a ...
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T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency = 2 T0 CLK COMMAND READ BANK, ADDRESS COL n DQ NOTE: Each READ command may be to any bank. DQM is LOW. 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 ...
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Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turn- around limitations). The WRITE burst ...
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A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not acti- vated), and a full-page burst may be truncated with a PRECHARGE command to the same ...
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PRECHARGE command is that it requires that the com- mand and address buses be available at the appropri- ate time to issue the command; the advantage of the PRECHARGE command is that it can be used to trun- cate fixed-length ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto ...
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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed- length WRITE burst may be immediately followed by a READ command. Once the READ command is regis- tered, the data inputs will ...
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Fixed-length or full-page WRITE bursts can be trun- cated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coin- cident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM ...
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CLOCK SUSPEND The clock suspend mode occurs when a column ac- cess/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “freezing” the synchronous logic. For each positive clock edge ...
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CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. ...
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WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank ...
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TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...
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TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L L ...
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...
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TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row L ...
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NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the ...
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ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V ....................................... -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (commercial) ....................................... ...
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CAPACITANCE (Note: 2; notes appear on page 37) PARAMETER - TSOP “TG” Package Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs PARAMETER - FBGA “FB” and “FG” Package Input Capacitance: CLK Input Capacitance: All other input-only ...
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AC FUNCTIONAL CHARACTERISTICS (Notes 11; notes appear on page 37) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to ...
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NOTES 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V dependent on output loading and cycle rates. DD Specified ...
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INITIALIZE AND LOAD MODE REGISTER CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH ( ( ) ) COMMAND NOP PRECHARGE ( ( ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMU A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM/ DQML, DQMU A0-A9, A11, A12 COLUMN ...
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T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMU A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all ...
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T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMU A0-A9, A11,A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all active banks ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ROW A10 DISABLE AUTO PRECHARGE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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SINGLE READ – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0-A9, A11,A12 ROW ROW A10 ...
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SINGLE READ – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0-A9, A11 ROW ROW A10 ...
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ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU COLUMN m 2 A0-A9, A11, A12 ROW ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU A0-A9, A11, A12 ROW ROW A10 DISABLE AUTO ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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SINGLE WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0-A9, A11 ROW ROW A10 ...
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SINGLE WRITE – WITH AUTO PRECHARGE CKS t CKH CKE t CMS t CMH NOP 4 COMMAND ACTIVE DQM/ DQML, DQMU A0-A9, A11, A12 ROW ...
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ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU A0-A9, A11, A12 ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ROW A10 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ROW A10 BA0, BA1 ...
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TYP .45 .30 PIN #1 ID .75 (2X) 1.00 (2X) NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per ...
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SEATING PLANE 0.10 0.45 ± 0.05 8.00 ±0.05 16.00 ±0.10 5.60 ±0.05 NOTE: 1. All dimensions in millimeters. 2. Recommended Pad size for PCB is 0.33mm±0.025mm. 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 FBGA “FB” PACKAGE ...
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SEATING PLANE C 0.10 C 54X ∅0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.33 BALL A9 6.40 3.20 ±0.05 3.20 ±0.05 NOTE: 1. All dimensions in millimeters. 2. Recommended Pad ...
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FBGA DEVICE MARKING Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks ...