MTD20N03HDL Freescale Semiconductor, Inc, MTD20N03HDL Datasheet

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MTD20N03HDL

Manufacturer Part Number
MTD20N03HDL
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
HDTMOS
High Density Power FET
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
 Motorola, Inc. 1995
MAXIMUM RATINGS
Motorola TMOS Power MOSFET Transistor Device Data
Drain–Source Voltage
Drain–Gate Voltage (R GS = 1.0 M )
Gate–Source Voltage — Continuous
Gate–Source Voltage
Drain Current — Continuous
Drain Current
Drain Current
Total Power Dissipation
Total Power Dissipation @ T C = 25 C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting T J = 25 C
Thermal Resistance — Junction to Case
Thermal Resistance
Thermal Resistance
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
This advanced HDTMOS power FET is designed to withstand
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
I DSS and V DS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Derate above 25 C
(V DD = 25 Vdc, V GS = 5.0 Vdc, Peak I L = 20 Apk, L = 1.0 mH, R G = 25 )
— Continuous @ 100 C
— Single Pulse (t p
— Junction to Ambient
— Junction to Ambient, when mounted with the minimum recommended pad size
— Non–Repetitive (t p
(T C = 25 C unless otherwise noted)
E-FET.
Data Sheet
10 s)
10 ms)
Rating
G
D
S
Symbol
T J , T stg
V DGR
V GSM
V DSS
R JC
R JA
R JA
V GS
MTD20N03HDL
E AS
I DM
P D
T L
I D
I D
R DS(on) = 0.035 OHM
CASE 369A–13, Style 2
TMOS POWER FET
Motorola Preferred Device
LOGIC LEVEL
20 AMPERES
30 VOLTS
– 55 to 150
Order this document
by MTD20N03HDL/D
DPAK
Value
1.75
1.67
71.4
200
100
260
0.6
30
30
20
16
60
74
15
20
Watts
W/ C
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
C/W
mJ
C
C
1

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MTD20N03HDL Summary of contents

Page 1

... Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 Motorola TMOS Power MOSFET Transistor Device Data  Motorola, Inc. 1995 D G Rating 10 ms) Order this document by MTD20N03HDL/D MTD20N03HDL Motorola Preferred Device TMOS POWER FET LOGIC LEVEL 20 AMPERES 30 VOLTS R DS(on) = 0.035 OHM  ...

Page 2

... MTD20N03HDL ELECTRICAL CHARACTERISTICS ( 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage ( Vdc 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current ( Vdc Vdc Vdc Vdc 125°C) Gate–Body Leakage Current ( ± ...

Page 3

... Figure 4. On–Resistance versus Drain Current 1000 100 10 1 100 125 150 DRAIN–TO–SOURCE VOLTAGE (Volts) Figure 6. Drain–To–Source Leakage MTD20N03HDL 100°C 25° – 55°C 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5 ...

Page 4

... MTD20N03HDL Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are deter- mined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculat- ing rise and fall because drain– ...

Page 5

... In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses 25°C 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0. SOURCE–TO–DRAIN VOLTAGE (Volts) MTD20N03HDL d(off) t d(on) 10 100 GATE RESISTANCE (Ohms) 0.95 1.0 5 ...

Page 6

... MTD20N03HDL The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is for- ward biased. Curves are based upon maximum peak junc- tion temperature and a case temperature ( 25°C. Peak ...

Page 7

... DUTY CYCLE 1.0E–03 1.0E–02 1.0E–01 t, TIME (s) Figure 14. Thermal Response di/ 0. Figure 15. Diode Reverse Recovery Waveform MTD20N03HDL R JC ( CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME J(pk) – (pk (t) 1.0E+00 1.0E+01 TIME 7 ...

Page 8

... MTD20N03HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface 0.190 4 ...

Page 9

... Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D 2 PAK is not recommended for wave soldering. MTD20N03HDL Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 10

... MTD20N03HDL For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next ...

Page 11

... Motorola TMOS Power MOSFET Transistor Device Data PACKAGE DIMENSIONS SEATING –T– PLANE STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE DRAIN CASE 369A–13 ISSUE W MTD20N03HDL NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.235 0.250 5.97 6.35 B ...

Page 12

... JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ 12 *MTD20N03HDL/D* Motorola TMOS Power MOSFET Transistor Device Data MTD20N03HDL/D ...

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