PI2EQX5804 Pericom Semiconductor, PI2EQX5804 Datasheet
PI2EQX5804
Available stocks
Related parts for PI2EQX5804
PI2EQX5804 Summary of contents
Page 1
... PCI-express signal before the re-driver, whereas the integrated de-emphasis circuitry provides fl exibility with signal integrity of the signal after the re-driver. In addition to providing signal re-conditioning, Pericom’s PI2EQX5804 also provides power management Stand-by mode operated by a Power Down pin. Pin Confi guration (Top-Side View) 2 ...
Page 2
... Selection pins for Channel Bx emphasis (See emphasis Confi gura- tion Table) w/ 100K-Ohm internal pull up I De-emphasis enable input for Channel A0, A1, A2 and A3 with internal 100K-Ohm pull-up resistor. Set high selects output de-em- phasis and set low selects output pre-emphasis. 2 PI2EQX5804 Equalization & Emphasis PS8926A 11/19/07 ...
Page 3
... Selection pins for Channel Bx output level (see Output Swing Con- fi guration Table) w/ 100K-Ohm internal pull up I/O I2C SCL clock input 3.3V input tolerance. I/O I2C SDA data input 3.3V input tolerance Selection pins for Channel Ax equalization (see Equalizer Confi gu- ration Table) w/ 100K-Ohm internal pull up 3 PI2EQX5804 Equalization & Emphasis PS8926A 11/19/07 ...
Page 4
... Table) w/ 100K-Ohm internal pull up O Signal detect output pin for Channel A0. SIG_A=High represents a input signal > threshold at the differential inputs. O Signal detect output pin for Channel B0. SIG_B=High represents a input signal > threshold at the differential inputs. PWR Supply Ground PWR 1.2V Supply Voltage 4 PI2EQX5804 Equalization & Emphasis PS8926A 11/19/07 ...
Page 5
... Output Confi guration The PI2EQX5804 provides fl exible output strength and emphasis controls to provide the optimum signal to pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output confi guration is grouped for the A and B channels, so that each channel within the group has the same setting. Output confi ...
Page 6
... Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5804 to confi gure itself properly depending on the devices it is communicating with, whether 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card ...
Page 7
... 50-Ohm pull- down 1 1 50-Ohm pull- down 7 PI2EQX5804 Equalization & Emphasis Mode Hi-Z Full IC power down, all chan- nels disabled Hi-Z No receiver (defi ned by PRSNT2#), all channels disabled 2K-Ohm pull-up Channel disabled, output pulls to Vdd. Receiver detect reset 2K-Ohm pull-up Channel enabled, no input signal, output pulls to Vdd ...
Page 8
... PCI Express Gen2 Re-Driver with Normal Operation Loopback Mode LB#= Mux Function Demux Function INDIS_BO = 1 ODIS_AO = 1 Solid: LB_A0B0#=1 Solid: Dashed: LB_A0B0#=0 Dashed: LB=1 Loopback Modes 8 PI2EQX5804 Equalization & Emphasis LB#= LB=0 PS8926A 11/19/07 ...
Page 9
... Power Down Control, enables power down for each channel individually 7 RXDE Receiver Detect Enable, controls the receiver detect operation 8 AEOC A-Channels Equalizer and Output Control 9 AEOC B-Channels Equalizer and Output Control 10 RSVD Reserved 11 RSVD Reserved 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with Equalization & Emphasis 9 PI2EQX5804 PS8926A 11/19/07 ...
Page 10
... For a write cycle, the fi rst data byte fol- lowing the address byte is a dummy or fi ll byte that is not used by the PI2EQX5804. This byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most signifi - cant bit (MSB) fi ...
Page 11
... RX50_A1 RX50_B1 LB_A2B2# LB_A3B3# R/W R/W R/W LB# LB# LB# 11 Equalization & Emphasis SIG_A2 SIG_B2 SIG_A3 RX50_A2 RX50_B2 RX50_A3 DE_A DE_B rsvd R/W R/W DE_A DE_B PS8926A PI2EQX5804 0 SIG_B3 RX50_B3 rsvd 11/19/07 ...
Page 12
... ODIS_A1 ODIS_B1 R/W R/W R RES_A1# RES_B1# RES_A2# R/W R/W RES_A# RES_B# 12 Equalization & Emphasis 3 2 INDIS_A2 INDIS_B2 INDIS_A3 R/W R/W R ODIS_A2 ODIS_B2 ODIS_ A3 R/W R/W R RES_B2# RES_A3# R/W R/W R/W RES_A# RES_B# RES_A# PS8926A PI2EQX5804 1 0 INDIS_ B3 R ODIS_ B3 R RES_B3# R/W RES_B# 11/19/07 ...
Page 13
... PD_A1# PD_B1# PD_A2# R/W R/W R/W PD# PD# PD RXD_A1 RXD_B1 RXD_A2 R/W R/W R/W RXD_A RXD_B RXD_A SEL2_A D0_A D1_A R/W R/W R/W SEL2_A D0_A D1_A 13 PI2EQX5804 Equalization & Emphasis PD_B2# PD_A3# PD_B3# R/W R/W R/W PD# PD# PD RXD_B2 RXD_A3 RXD_B3 R/W R/W R/W RXD_B RXD_A RXD_B D2_A S0_A S1_A R/W R/W R/W D2_A ...
Page 14
... HIGH transition on the SDA line while SCL is HIGH defi nes a STOP condition, as shown in the fi gure below. 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with SEL2_B D0_B D1_B R/W R/W R/W SEL2_B D0_B D1_B PI2EQX5804 Equalization & Emphasis D2_B S0_B S1_B R/W R/W R/W D2_B S0_B S1_B PS8926A 11/19/07 ...
Page 15
... I2C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. 15 Equalization & Emphasis ACK NO ACK DATA OUT N ACK ACK DATA IN N DATA OUT N DATA OUT 1 ACK ACK PS8926A PI2EQX5804 ACK NO 11/19/07 ...
Page 16
... A Conditions = 0 TO 70°C) A Conditions 16 PI2EQX5804 Equalization & Emphasis Note: Stresses greater than those listed under MAXI- MUM RATINGS may cause permanent damage to the device. This is a stress rating only and function al operation of the device at these or any other condi- tions above those indicated in the operational sections of this specifi ...
Page 17
... Conditions Total Deterministic Note 70°C) A Conditions Single ended |VTX-D+ - VTX-D-| VTX-DIFFP VTX VTX-D- | 20% to 80% ( 70°C) A Conditions I = 4mA 4mA OL 17 PI2EQX5804 Equalization & Emphasis Min. Typ. Max. 0.3 0.2 1.5 Min. Typ. Max 100 120 200 800 0.4 1.6 VDD- ...
Page 18
... Typ. Max. 0 100 4.0 – 4.7 – 4.0 – 4.7 – 5.0 – 250 – – 100 300 4.0 – 4.7 – – 400 of the SCL signal) to bridge the undefi ned IHmin PS8926A PI2EQX5804 Units Unit kHz μs μs μs μs μ μs μs pF 11/19/07 ...
Page 19
... START SDA t SU;DAT LOW SCL t HD;STA t HD;DAT S 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with HD;STA t SU;STA HIGH Sr I2C Timing Channel Latency, 5.0 Gbps 19 PI2EQX5804 Equalization & Emphasis STOP START BUF t SU;STO P S PS8926A 11/19/07 ...
Page 20
... Output Level Settings (1V left, and 0.5V right at 5.0 Gbps) 0.0 dB (Dx = 000) –6.5 dB (Dx = 101) Output De-emphasis Characteristics 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with Equalization & Emphasis –3.5 dB (Dx = 010) –8.5 dB (Dx = 111) 20 PI2EQX5804 PS8926A 11/19/07 ...
Page 21
... Eye Diagrams 5.0Gbps (input left, output right) Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right) Signal Source Connector AC Test Circuit Referenced in the Electrical Characteristic Table 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with FR4 A B SmA SmA Connector ≤ PI2EQX5804 Equalization & Emphasis C D.U.T. In Out PS8926A 11/19/07 ...
Page 22
... Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with DESCRIPTION: 100-Ball Low Profile Ball Grid Array (LBGA) PACKAGE CODE: NJ100 DOCUMENT CONTROL #: PD-2055 Package Code Package Description NJ Pb-free & Green 100-Contact LFBGA 22 PI2EQX5804 Equalization & Emphasis DATE: 06/11/07 REVISION: A PS8926A 11/19/07 ...