PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 101/202:

AUTO-BAUD DETECT

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10.3.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCTL register starts
the auto-boot sequence (Figure 10-6). While the ABD
sequence takes place, the EUSART state machine is
held in Idle. On the first rising edge of the receive line,
after the Start bit, the SPBRG begins counting up using
the BRG counter clock as shown in Table 10-6. The
fifth rising edge will occur on the RX pin at the end of
the eighth bit period. At that time, an accumulated
value totaling the proper BRG period is left in
SPBRGH, SPBRG register pair, the ABDEN bit is
automatically cleared and the RCIF interrupt flag is set.
The value in the RCREG needs to be read to clear the
RCIF interrupt. RCREG content should be discarded.
When calibrating for modes that do not use the
SPBRGH register the user can verify that the SPBRG
register did not overflow by checking for 00h in the
SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 10-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
FIGURE 10-6:
AUTOMATIC BAUD RATE CALCULATION
XXXXh
0000h
BRG Value
RX pin
BRG Clock
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRG
SPBRGH
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
© 2007 Microchip Technology Inc.
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 10.3.2
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system timing
and communication baud rates must be
taken into consideration when using the
Auto-Baud Detect feature.
3: During the auto-baud process, the auto-
baud counter starts counting at 1. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract 1
from the SPBRGH:SPBRG register pair.
TABLE 10-6:
BRG16
BRGH
0
0
0
1
1
0
1
1
Note:
During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
Edge #2
Edge #1
Edge #3
bit 1
bit 3
Start
bit 0
bit 2
bit 4
XXh
XXh
PIC16F688
“Auto-Wake-up
on
BRG COUNTER CLOCK RATES
BRG Base
BRG ABD
Clock
Clock
F
/64
F
/512
OSC
OSC
F
/16
F
/128
OSC
OSC
F
/16
F
/128
OSC
OSC
F
/4
F
/32
OSC
OSC
001Ch
Edge #4
Edge #5
bit 5
bit 7
bit 6
Stop bit
Auto Cleared
1Ch
00h
DS41203D-page 99