PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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PIC16F688
TABLE 2-2:
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr
Name
Bit 7
Bit 6
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
81h
OPTION_REG
RAPU
INTEDG
82h
PCL
Program Counter’s (PC) Least Significant Byte
83h
STATUS
IRP
RP1
84h
FSR
Indirect Data Memory Address Pointer
85h
TRISA
86h
Unimplemented
87h
TRISC
88h
Unimplemented
89h
Unimplemented
8Ah
PCLATH
8Bh
INTCON
GIE
PEIE
8Ch
PIE1
EEIE
ADIE
8Dh
Unimplemented
8Eh
PCON
8Fh
OSCCON
IRCF2
90h
OSCTUNE
91h
ANSEL
ANS7
ANS6
92h
Unimplemented
93h
Unimplemented
94h
Unimplemented
(2)
95h
WPUA
96h
IOCA
97h
EEDATH
98h
EEADRH
99h
VRCON
VREN
9Ah
EEDAT
EEDAT7
EEDAT6
9Bh
EEADR
EEADR7 EEADR6
9Ch
EECON1
EEPGD
9Dh
EECON2
EEPROM Control 2 Register (not a physical register)
9Eh
ADRESL
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
9Fh
ADCON1
ADCS2
Legend:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note
1:
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2:
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
3:
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
DS41203D-page 10
Bit 5
Bit 4
Bit 3
Bit 2
T0CS
T0SE
PSA
PS2
RP0
TO
PD
Z
TRISA5
TRISA4
TRISA3
TRISA2
TRISC5
TRISC4
TRISC3
TRISC2
Write Buffer for upper 5 bits of Program Counter
T0IE
INTE
RAIE
T0IF
RCIE
C2IE
C1IE
OSFIE
ULPWUE
SBOREN
IRCF1
IRCF0
OSTS
HTS
TUN4
TUN3
TUN2
ANS5
ANS4
ANS3
ANS2
WPUA5
WPUA4
WPUA2
IOCA5
IOCA4
IOCA3
IOCA2
EEDATH5
EEDATH4 EEDATH3 EEDATH2
EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000
VRR
VR3
VR2
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEADR5
EEADR4
EEADR3
EEADR2
WRERR
WREN
ADCS1
ADCS0
Value on
Bit 1
Bit 0
Page
POR/BOR
20, 117
xxxx xxxx
PS1
PS0
14, 117
1111 1111
19, 117
0000 0000
DC
C
13, 117
0001 1xxx
20, 117
xxxx xxxx
TRISA1
TRISA0
33, 117
--11 1111
TRISC1
TRISC0
42, 117
--11 1111
19, 117
---0 0000
(3)
INTF
RAIF
15, 117
0000 000x
TXIE
TMR1IE
16, 117
0000 0000
POR
BOR
18, 117
--01 --qq
LTS
SCS
22, 118
-110 x000
TUN1
TUN0
26, 118
---0 0000
ANS1
ANS0
34, 118
1111 1111
WPUA1
WPUA0
35, 118
--11 -111
IOCA1
IOCA0
35, 118
--00 0000
EEDATH1 EEDATH0
78, 118
--00 0000
78, 118
VR1
VR0
63, 118
0-0- 0000
EEDAT1
EEDAT0
78, 118
0000 0000
EEADR1
EEADR0
78, 118
0000 0000
WR
RD
79, 118
x--- x000
77, 118
---- ----
72, 118
xxxx xxxx
71, 118
-000 ----
© 2007 Microchip Technology Inc.