PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 122/202:

RA2/INT INTERRUPT

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PIC16F688
11.3.1

RA2/INT INTERRUPT

External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit of the OPTION register is
set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RA2/INT pin, the INTF bit of the
INTCON register is set. This interrupt can be disabled
by clearing the INTE control bit of the INTCON register.
The INTF bit must be cleared in software in the Inter-
rupt Service Routine before re-enabling this interrupt.
The RA2/INT interrupt can wake-up the processor from
Sleep if the INTE bit was set prior to going into Sleep.
The status of the GIE bit decides whether or not the
processor branches to the interrupt vector following
wake-up (0004h). See Section 11.6 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 11-10
for timing of wake-up from Sleep through RA2/INT
interrupt.
Note:
The ANSEL (91h) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
FIGURE 11-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
TXIF
TXIE
TMR1IF
TMR1IE
C1IF
C1IE
C2IF
C2IE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
RCIF
RCIE
DS41203D-page 120
11.3.2
TIMER0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF of the INTCON register bit. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
11.3.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF bit of
the INTCON register. The interrupt can be enabled/dis-
abled by setting/clearing the RAIE bit of the INTCON
register. Plus, individual pins can be configured through
the IOCA register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
T0IF
T0IE
INTF
INTE
RAIF
RAIE
PEIE
GIE
© 2007 Microchip Technology Inc.
Interrupt to CPU