PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 123/202

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FIGURE 11-8:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(5)
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
PC
Instruction
Inst (PC)
Fetched
Instruction
Inst (PC - 1)
Executed
Note 1:
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-4 T
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
3:
CLKOUT is available only in INTOSC and RC Oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 14.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 11-6:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
INTCON
GIE
PEIE
T0IE
PIE1
EEIE
ADIE
RCIE
PIR1
EEIF
ADIF
RCIF
Legend:
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
© 2007 Microchip Technology Inc.
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
(1)
(2)
Interrupt Latency
PC + 1
PC + 1
Inst (PC + 1)
Dummy Cycle
Dummy Cycle
Inst (PC)
. Synchronous latency = 3 T
, where T
CY
CY
Bit 4
Bit 3
Bit 2
Bit 1
INTE
RAIE
T0IF
INTF
C2IE
C1IE
OSFIE
TXIE
C2IF
C1IF
OSFIF
TXIF
PIC16F688
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0004h
0005h
Inst (0004h)
Inst (0005h)
Inst (0004h)
= instruction cycle time.
CY
Value on
Value on
Bit 0
all other
POR, BOR
Resets
RAIF
0000 000x
0000 000x
TMR1IE
0000 0000
0000 0000
TMR1IF
0000 0000
0000 0000
DS41203D-page 121