PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 
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Page 128/202:

Code Protection

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PIC16F688
FIGURE 11-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
(4)
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
PC
PC + 1
Instruction
Inst(PC + 1)
Inst(PC) = Sleep
Fetched
Instruction
Sleep
Inst(PC - 1)
Executed
Note
1:
XT, HS or LP Oscillator mode assumed.
2:
T
= 1024 T
(drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
OST
OSC
3:
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4:
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
11.7

Code Protection

If
the
code
protection
bit(s)
have
programmed, the on-chip program memory can be
read out using ICSP for verification purposes.
Note:
The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
11.8
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
DS41203D-page 126
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OST (2)
T
(3)
Interrupt Latency
Processor in
Sleep
PC + 2
PC + 2
PC + 2
Inst(PC + 2)
Inst(PC + 1)
Dummy Cycle
not
been
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
© 2007 Microchip Technology Inc.