PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 49/202

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REGISTER 5-1:
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
bit 7
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
bit 7
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
BIT VALUE
000
001
010
011
100
101
110
111
Note 1:
A dedicated 16-bit WDT postscaler is available. See Section 11.5 “Watchdog Timer (WDT)” for more
information.
TABLE 5-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
TMR0
Timer0 Module Register
INTCON
GIE
PEIE
T0IE
OPTION_REG
RAPU INTEDG
T0CS
TRISA
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
© 2007 Microchip Technology Inc.
R/W-1
R/W-1
T0SE
PSA
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
/4)
OSC
TMR0 RATE
WDT RATE
1 : 2
1 : 1
1 : 4
1 : 2
1 : 8
1 : 4
1 : 16
1 : 8
1 : 32
1 : 16
1 : 64
1 : 32
1 : 128
1 : 64
1 : 256
1 : 128
Bit 4
Bit 3
Bit 2
Bit 1
INTE
RAIE
T0IF
INTF
T0SE
PSA
PS2
PS1
PIC16F688
R/W-1
R/W-1
R/W-1
PS2
PS1
PS0
bit 0
x = Bit is unknown
Value on
Value on
Bit 0
all other
POR, BOR
Resets
xxxx xxxx uuuu uuuu
RAIF
0000 000x 0000 000x
PS0
1111 1111 1111 1111
DS41203D-page 47