PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
Page 64/202:

Comparator C2 Gating Timer1

Download datasheet (4Mb)Embed
PrevNext
PIC16F688
7.8

Comparator C2 Gating Timer1

This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of Comparator C2. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize Comparator C2 with
Timer1 by setting the C2SYNC bit when the comparator
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if the comparator changes
during an increment.
REGISTER 7-2:
CMCON1: COMPARATOR CONFIGURATION REGISTER
U-0
U-0
U-0
bit 7
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
bit 7-2
Unimplemented: Read as ‘0’
bit 1
T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is T1G pin (pin should be configured as digital input)
0 = Timer1 gate source is Comparator C2 output
bit 0
C2SYNC: Comparator C2 Output Synchronization bit
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
Note 1:
Refer to Section 6.6 “Timer1 Gate”.
2:
Refer to Figure 7-3.
DS41203D-page 62
7.9
Synchronizing Comparator C2
Output to Timer1
The output of Comparator C2 can be synchronized with
Timer1 by setting the C2SYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. Reference the comparator block diagrams
(Figure 7-2 and Figure 7-3) and the Timer1 Block
Diagram (Figure 6-1) for more information.
U-0
U-0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
(2)
© 2007 Microchip Technology Inc.
R/W-1
R/W-0
T1GSS
C2SYNC
bit 0
x = Bit is unknown