PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 82/202:

READING THE DATA EEPROM MEMORY

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PIC16F688
9.1.2
READING THE DATA EEPROM
MEMORY
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit of the EECON1 register, and then set control
bit RD of the EECON1 register. The data is available in
the very next cycle, in the EEDAT register; therefore, it
can be read in the next instruction. EEDAT will hold this
value until another read or until it is written to by the
user (during a write operation).
EXAMPLE 9-1:
DATA EEPROM READ
BANKSEL EEADR
;
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
;Data Memory
;Address to read
BCF
EECON1, EEPGD
;Point to DATA
;memory
BSF
EECON1, RD
;EE Read
MOVF
EEDAT, W
;W = EEDAT
EXAMPLE 9-2:
DATA EEPROM WRITE
BANKSEL EEADR
MOVLW
DATA_EE_ADDR
MOVWF
EEADR
MOVLW
DATA_EE_DATA
MOVWF
EEDAT
BANKSEL EECON1
BCF
EECON1, EEPGD
BSF
EECON1, WREN
BCF
INTCON, GIE
BTFSC
INTCON, GIE
GOTO
$-2
MOVLW
55h
MOVWF
EECON2
MOVLW
AAh
MOVWF
EECON2
BSF
EECON1, WR
BSF
INTCON, GIE
SLEEP
BCF
EECON1, WREN
DS41203D-page 80
9.1.3
WRITING TO THE DATA EEPROM
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;
;Point to DATA memory
;Enable writes
;Disable INTs.
;SEE AN576
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable INTs.
;Wait for interrupt to signal write complete
;Disable writes
© 2007 Microchip Technology Inc.