PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 85/202:

ENHANCED UNIVERSAL

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10.0

ENHANCED UNIVERSAL

SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
Full-Duplex
mode
is
communications with peripheral systems, such as CRT
terminals
and
personal
computers.
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 10-1:
EUSART TRANSMIT BLOCK DIAGRAM
TXEN
Baud Rate Generator
F
OSC
÷ n
n
BRG16
+ 1
Multiplier
x4
SYNC
1 X 0 0
SPBRGH
SPBRG
BRGH
X 1 1 0
BRG16
X 1 0 1
© 2007 Microchip Technology Inc.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
The EUSART module implements the following
useful
for
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
Half-Duplex
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 10-1 and Figure 10-2.
Data Bus
TXREG Register
8
MSb
(8)
• • •
Transmit Shift Register (TSR)
TRMT
TX9
x16 x64
TX9D
0
0
0
PIC16F688
TXIE
Interrupt
TXIF
TX/CK pin
LSb
Pin Buffer
0
and Control
SPEN
DS41203D-page 83