PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 
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Page 9/202:

MEMORY ORGANIZATION

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2.0

MEMORY ORGANIZATION

2.1
Program Memory Organization
The PIC16F688 has a 13-bit program counter capable
of addressing a 4K x 14 program memory space. Only
the first 4K x 14 (0000h-01FFF) for the PIC16F688 is
physically implemented. Accessing a location above
these boundaries will cause a wraparound within the
first 4K x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F688
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
Wraps to 0000h-07FFh
© 2007 Microchip Technology Inc.
2.2
Data Memory Organization
The data memory is partitioned into multiple banks,
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP0
and RP1 are bank select bits.
RP1
RP0
0
0
0
1
1
0
1
1
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are the General Purpose Registers, implemented
as static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank are mirrored in
another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 256 x 8 in the
PIC16F688. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
0000h
(see Section 2.4 “Indirect Addressing, INDF and
FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
0004h
The Special Function Registers are registers used by
0005h
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1, 2-2,
2-3 and 2-4). These registers are static RAM.
01FFh
The special registers can be classified into two sets:
02000h
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
1FFFh
feature.
PIC16F688
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
DS41203D-page 7