PIC16F690 Microchip Technology Inc., PIC16F690 Datasheet

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PIC16F690

Manufacturer Part Number
PIC16F690
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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PIC16F631/677/685/687/689/690
Data Sheet
20-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
© 2007 Microchip Technology Inc.
DS41262D

Related parts for PIC16F690

PIC16F690 Summary of contents

Page 1

... PIC16F631/677/685/687/689/690 © 2007 Microchip Technology Inc. Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41262D ...

Page 2

... EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified logo, microID, MPLAB, PIC DSCs ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ® ...

Page 3

... EEPROM endurance - Flash/Data EEPROM retention: > 40 years • Enhanced USART module: - Supports RS-485, RS-232 and LIN 2.0 - Auto-Baud Detect - Auto-wake-up on Start bit © 2007 Microchip Technology Inc. nanoWatt Technology Low-Power Features: • Standby Current 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 220 μ ...

Page 4

... PIC16F677 2048 128 256 PIC16F685 4096 256 256 PIC16F687 2048 128 256 PIC16F689 4096 256 256 PIC16F690 4096 256 256 PIC16F631 Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT RC3/C12IN3- TABLE 1: PIC16F631 PIN SUMMARY I/O Pin Analog Comparators RA0 ...

Page 5

... C12IN3- RC4 6 — C2OUT RC5 5 — RC6 8 AN8 RC7 9 AN9 — 1 — — 20 — Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc RA0/AN0/C1IN+/ICSPDAT/ULPWU 19 3 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT 17 RC5 5 16 RC0/AN4/C2IN ...

Page 6

... IOC Y — IOC Y — IOC Y — — — — — — — — — — — — — — — — — — — — — — — — — — — — — © 2007 Microchip Technology Inc. ...

Page 7

... RC5 5 — — RC6 8 AN8 — RC7 9 AN9 — — 1 — — — 20 — — Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc RA0/AN0/C1IN+/ICSPDAT/ULPWU 3 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT PP 17 RC5 5 16 RC0/AN4/C2IN+ ...

Page 8

... PIC16F631/677/685/687/689/690 PIC16F690 Pin Diagram (PDIP, SOIC, SSOP) 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK TABLE 5: PIC16F690 PIN SUMMARY I/O Pin Analog Comparators Timers RA0 19 AN0/ULPWU C1IN+ RA1 18 AN1/V C12IN0- REF RA2 17 AN2 C1OUT RA3 4 — ...

Page 9

... RA3/MCLR/V PP (1) RC5/CCP1/P1A (1) RC4/C2OUT/P1B (1) RC3/AN7/C12IN3-/P1C (2) RC6/AN8/SS Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only. 2: SS, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT PIC16F631/677/ ...

Page 10

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41262D-page 8 © 2007 Microchip Technology Inc. ...

Page 11

... Microchip Technology Inc. Block Diagrams and pinout descriptions of the devices are as follows: • PIC16F631 (Figure 1-1, Table 1-1) • PIC16F677 (Figure 1-2, Table 1-2) • PIC16F685 (Figure 1-3, Table 1-3) • PIC16F687/PIC16F689 (Figure 1-4, Table 1-4) • PIC16F690 (Figure 1-5, Table 1-5) INT 8 Data Bus RAM 64 bytes File Registers ...

Page 12

... C2IN- C2IN+ C2OUT 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5 PORTB RB4 RB5 RB6 RB7 PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 SDI/ SCK/ SS SDO SDA SCL Synchronous Serial Port EEDAT 256 Bytes 8 Data EEPROM EEADR © 2007 Microchip Technology Inc. ...

Page 13

... T0CKI ULPWU Ultra Low-Power Timer0 Wake-up AN8 AN9 AN10 AN11 Analog-To-Digital Converter V AN0 AN1 AN2 AN3 AN4 AN5 AN6 REF © 2007 Microchip Technology Inc. INT Data Bus Program Counter RAM 8-Level Stack (13-bit) 256 bytes File Registers RAM Addr ...

Page 14

... C2IN- C2IN+ C2OUT 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5 PORTB RB4 RB5 RB6 RB7 PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 SDI/ SCK/ SDA SCL SS SDO Synchronous Serial Port EEDAT 256 Bytes 8 Data EEPROM EEADR © 2007 Microchip Technology Inc. ...

Page 15

... PIC16F631/677/685/687/689/690 FIGURE 1-5: PIC16F690 BLOCK DIAGRAM Configuration 13 Program Counter Flash Program 8-Level Stack (13-bit) Memory Program 14 Bus Instruction Reg Direct Addr 8 Power-up Instruction Oscillator Decode and Start-up Timer Control OSC1/CLKI Power-on Timing OSC2/CLKO Watchdog Generation Brown-out Internal Oscillator Block MCLR T1G ...

Page 16

... Comparator inverting input. ST CMOS General purpose I/O. AN — Comparator inverting input. ST CMOS General purpose I/O. — CMOS Comparator C2 output. ST CMOS General purpose I/O. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description © 2007 Microchip Technology Inc. ...

Page 17

... RC7 Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. Input Output Type Type ST CMOS General purpose I/O. ST CMOS General purpose I/O. Power — Ground reference. Power — Positive supply. CMOS = CMOS compatible input or output ...

Page 18

... Individually enabled pull-up. AN — A/D Channel 11 input. TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ST CMOS SPI clock C™ clock. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description © 2007 Microchip Technology Inc. ...

Page 19

... Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ST CMOS General purpose I/O. AN — A/D Channel 4 input. AN — ...

Page 20

... Individually enabled pull-up. TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. ST CMOS General purpose I/O. AN — A/D Channel 4 input. AN — Comparator C2 positive input. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description © 2007 Microchip Technology Inc. ...

Page 21

... RC7/AN9 RC7 AN9 Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. Input Output Type Type ST CMOS General purpose I/O. AN — A/D Channel 5 input. AN — Comparator negative input. ST CMOS General purpose I/O. AN — ...

Page 22

... CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN — A/D Channel 11 input. ST — EUSART asynchronous input. ST CMOS EUSART synchronous data. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description OD = Open Drain © 2007 Microchip Technology Inc. ...

Page 23

... Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. ST CMOS SPI clock C™ clock. ...

Page 24

... PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 Name Function RA0/AN0/C1IN+/ICSPDAT/ RA0 ULPWU AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/V /ICSPCLK RA1 REF AN1 C12IN0- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V PP RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN ...

Page 25

... PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED) Name Function RB6/SCK/SCL RB6 SCK SCL RB7/TX/CK RB7 TX CK RC0/AN4/C2IN+ RC0 AN4 C2IN+ RC1/AN5/C12IN1- RC1 AN5 C12IN1- RC2/AN6/C12IN2-/P1D RC2 AN6 C12IN2- P1D RC3/AN7/C12IN3-/P1C RC3 AN7 C12IN3- P1C RC4/C2OUT/P1B RC4 C2OUT P1B RC5/CCP1/P1A ...

Page 26

... PIC16F631/677/685/687/689/690 NOTES: DS41262D-page 24 © 2007 Microchip Technology Inc. ...

Page 27

... PIC16F631, the first (0000h-07FFh) for the PIC16F677/PIC16F687, and the (0000h-0FFFh) for the PIC16F685/PIC16F689/ PIC16F690. Accessing a location above these boundaries will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1 through 2-3). FIGURE 2-1: PROGRAM MEMORY MAP ...

Page 28

... GENERAL PURPOSE REGISTER FILE The register file is organized as 128 the 1FFFh PIC16F687 PIC16F685/PIC16F689/PIC16F690. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by ...

Page 29

... Purpose Registers 6Fh 64 Bytes 70h accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. File File Address Address (1) (1) 80h Indirect addr. 100h TMR0 101h 82h PCL 102h ...

Page 30

... PCLATH 18Ah INTCON 18Bh EECON1 18Ch (1) EECON2 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh SRCON 19Eh 19Fh 1A0h 1EFh accesses 1F0h 70h-7Fh 1FFh Bank 3 © 2007 Microchip Technology Inc. ...

Page 31

... Purpose Purpose Register Register 80 Bytes 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. File File Address Address (1) (1) 80h Indirect addr. 100h TMR0 101h 82h PCL 102h ...

Page 32

... PCLATH 18Ah INTCON 18Bh EECON1 18Ch (1) EECON2 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh SRCON 19Eh 19Fh 1A0h accesses 1F0h 70h-7Fh 1FFh Bank 3 © 2007 Microchip Technology Inc. ...

Page 33

... PIC16F631/677/685/687/689/690 FIGURE 2-8: PIC16F690 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH INTCON ...

Page 34

... PIC16F685/PIC16F690 only. 4: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 6: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register. See Registers 13-2 and 13-3 for more detail. 7: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets) ...

Page 35

... MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F687/PIC16F689/PIC16F690 only. 3: PIC16F685/PIC16F690 only. 4: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 6: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word. 7: Accessible only when SSPCON register bits SSPM<3:0> = 1001. © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...

Page 36

... MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. 4: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). DS41262D-page 34 ...

Page 37

... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F685/PIC16F690 only. © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 38

... Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (ADDWF, ADDLW, SUBLW, SUBWF instructions) R/W-x R/W-x R/W-x (1) ( bit Bit is unknown (1) (1) © 2007 Microchip Technology Inc. ...

Page 39

... Bit Value 000 001 010 011 100 101 110 111 © 2007 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 6.3 “Timer1 Prescaler”. R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘ ...

Page 40

... GIE of the INTCON register. User software appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1,3) (2) INTE RABIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,3) (2) should ensure the R/W-0 R/W-x INTF RABIF bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 41

... Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F685/PIC16F690 only. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F687/PIC16F689/PIC16F690 only. 4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 (3) (3) (4) TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...

Page 42

... Unimplemented: Read as ‘0’ DS41262D-page 40 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 U-0 U-0 EEIE — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 43

... PIC16F685/PIC16F690 only. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F687/PIC16F689/PIC16F690 only. 4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User appropriate interrupt flag bits are clear prior to enabling an interrupt ...

Page 44

... GIE of the INTCON register. User software appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 U-0 U-0 EEIF — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 45

... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> the Configuration Word register for this bit to control the BOR. © 2007 Microchip Technology Inc. R/W-1 U-0 U-0 (1) SBOREN — ...

Page 46

... A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue © 2007 Microchip Technology Inc. ...

Page 47

... DIRECT/INDIRECT ADDRESSING PIC16F631/677/685/687/689/690 Direct Addressing From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figures 2-6, 2-7 and 2-8. © 2007 Microchip Technology Inc. 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 Indirect Addressing ...

Page 48

... PIC16F631/677/685/687/689/690 NOTES: DS41262D-page 46 © 2007 Microchip Technology Inc. ...

Page 49

... OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...

Page 50

... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. DS41262D-page 48 R/W-0 R-1 R-0 (1) IRCF0 OSTS HTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R/W-0 LTS SCS bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 51

... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. 3.4 External Clock Modes 3.4.1 OSCILLATOR START-UP TIMER (OST) ...

Page 52

... DD ® ® and PIC ® Oscillator Design” ® Oscillator CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic ( Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode © 2007 Microchip Technology Inc. ...

Page 53

... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. 3.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...

Page 54

... Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 55

... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. 3.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6) ...

Page 56

... HFINTOSC LFINTOSC ≠ IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <2:0> System Clock DS41262D-page 54 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ¼ 0 Running Running Running © 2007 Microchip Technology Inc. ...

Page 57

... Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)” ...

Page 58

... FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC T T OST OSC1 1022 1023 0 1 OSC2 Program Counter System Clock DS41262D-page © 2007 Microchip Technology Inc. ...

Page 59

... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...

Page 60

... TXIF SSPIF CCP1IF TMR2IF Failure Detected Test Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 — — SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu TMR1IE -000 0000 -000 0000 TMR1IF -000 0000 -000 0000 © 2007 Microchip Technology Inc. ...

Page 61

... Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2007 Microchip Technology Inc. port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. The TRISA register controls the PORTA pin output drivers, even when they are being used as analog inputs ...

Page 62

... Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Note change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RABIF interrupt flag may not get set. © 2007 Microchip Technology Inc. ...

Page 63

... Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 ...

Page 64

... WPUA4 — WPUA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 IOCA4 IOCA3 IOCA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 WPUA1 WPUA0 bit Bit is unknown R/W-0 R/W-0 IOCA1 IOCA0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 65

... RC circuit on RA0. See Example 4-2 for initializing the Ultra Low-Power Wake-up module. © 2007 Microchip Technology Inc. A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/AN0/C1IN+/ICSPDAT/ULPWU pin and can allow for software calibration of the time-out (see Figure 4-1) ...

Page 66

... In-Circuit Serial Programming™ data • an analog input for the Ultra Low-Power Wake-up (1) Analog Input Mode RABPU - + 0 1 (1) Analog Input Mode ULPWUE PORTA To Comparator (2) To A/D Converter V DD Weak V DD I/O Pin ULP V SS © 2007 Microchip Technology Inc. ...

Page 67

... RD PORTA To Comparator (2) To A/D Converter Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. © 2007 Microchip Technology Inc. /ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT Figure 4-3 shows the diagram for this pin. The RA2/AN2/T0CKI/INT/C1OUT pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • ...

Page 68

... BLOCK DIAGRAM OF RA4 (3) Analog Input Mode (1) CLK Modes Weak RABPU Oscillator Circuit OSC1 V DD CLKOUT Enable F /4 OSC I/O Pin Q CLKOUT Enable INTOSC/ (2) RC/EC Q CLKOUT Enable Analog Input Mode PORTA (4) © 2007 Microchip Technology Inc. ...

Page 69

... Mode TRISA RD PORTA IOCA EN RD IOCA Interrupt-on- Change RD PORTA To TMR1 or CLKGEN Note 1: Timer1 LP Oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. © 2007 Microchip Technology Inc Weak V DD I/O Pin V SS (2) Q3 DS41262D-page 67 ...

Page 70

... RABIF 0000 000x 0000 000x IOCA0 --00 0000 --00 0000 PS0 1111 1111 1111 1111 RA0 --xx xxxx --uu uuuu SSPM0 0000 0000 0000 0000 TMR1ON 0000 0000 uuuu uuuu TRISA0 --11 1111 --11 1111 WPUA0 --11 -111 --11 -111 © 2007 Microchip Technology Inc. ...

Page 71

... Port pin is > Port pin is < bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. 4.4.1 WEAK PULL-UPS Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:4> enable or disable each pull-up (see Register 4-9). Each weak pull up is automatically turned off when the port pin is configured as an output ...

Page 72

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 U-0 IOCB4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 73

... TRISB (1) Analog RD Input Mode TRISB RD PORTB IOCB EN RD IOCB Interrupt-on- Change RD PORTB To SSPSR (2) To A/D Converter Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. DS41262D-page 71 available Weak V DD I/O Pin ...

Page 74

... WPUB RD WPUB available PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change To EUSART RX/DT To A/D Converter Available on PIC16F687/PIC16F689/PIC16F690 only. Note 1: 2: BLOCK DIAGRAM OF RB5 (1) Analog Input Mode Weak RABPU SYNC SPEN EUSART I/O Pin From ...

Page 75

... Data Bus WPUB RD WPUB available PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change To SSPSR Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. BLOCK DIAGRAM OF RB6 Weak RABPU SSPEN SSP Clock I/O Pin From Q SSP ...

Page 76

... Data Bus WPUB RD WPUB available PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change Available on PIC16F687/PIC16F689/PIC16F690 only. BLOCK DIAGRAM OF RB7 Weak RABPU SPEN TXEN SYNC EUSART EUSART I/O Pin Q ‘1’ ...

Page 77

... PORTB RB7 RB6 RB5 TRISB TRISB7 TRISB6 TRISB5 TRISB4 WPUB WPUB7 WPUB6 WPUB5 WPUB4 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 IOCB4 — — — ...

Page 78

... TRISC4 TRISC3 TRISC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ;Bank 0 ; ;Init PORTC ;Bank 2 ;digital I/O ;Bank 1 ; ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0 R/W-x R/W-x RC1 RC0 bit Bit is unknown R/W-1 R/W-1 TRISC1 TRISC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 79

... SS Data Bus PORTC TRISC RD TRISC RD PORTC To Comparators To A/D Converter Available on PIC16F685/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. (1) is configurable to function as (1) is configurable to function as one BLOCK DIAGRAM OF RC2 AND RC3 CCP1OUT Enable CCP1OUT ...

Page 80

... Data bus PORTC TRISC RD TRISC I/O Pin RD PORTC To Enhanced CCP V SS Available on PIC16F685/PIC16F690 only. (1) is configurable to function as and P1A are available on BLOCK DIAGRAM OF RC5 CCP1OUT Enable V DD CCP1OUT I/O Pin V SS © 2007 Microchip Technology Inc. ...

Page 81

... V DD Data Bus I/O Pin Q PORTC TRISC RD TRISC RD PORTC To A/D Converter Available on PIC16F685/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. (1,2) is configurable to function as BLOCK DIAGRAM OF RC7 PORT/SDO Select SDO I/O Pin V SS Analog Input (1) ...

Page 82

... TRISC TRISC7 TRISC6 TRISC5 VRCON C1VREN C2VREN VRR Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: PIC16F687/PIC16F689/PIC16F690 only. 2: PIC16F685/PIC16F690 only. DS41262D-page 80 Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 — ANS11 ANS10 ANS9 ...

Page 83

... T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...

Page 84

... T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements Section 17.0 “Electrical Specifications”. © 2007 Microchip Technology Inc. as shown in ...

Page 85

... TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 86

... Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function (PIC16F685/PIC16F690 only) • Special Event Trigger (with ECCP) (PIC16F685/PIC16F690 only) • Comparator output synchronization to Timer1 clock Figure 6 block diagram of the Timer1 module. FIGURE 6-1: TIMER1 BLOCK DIAGRAM ...

Page 87

... LP mode. The user must provide a software time delay to ensure proper oscillator start-up. © 2007 Microchip Technology Inc. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as ‘0’ and TRISA5 and TRISA4 bits read as ‘ ...

Page 88

... Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see “Synchronizing Comparator C2 output to Timer1”. © 2007 Microchip Technology Inc. to utilize OSC Section 8.8.2 ...

Page 89

... PIC16F631/677/685/687/689/690 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. DS41262D-page 87 ...

Page 90

... TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. DS41262D-page 88 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /4) R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 91

... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 — — ...

Page 92

... PIC16F631/677/685/687/689/690 NOTES: DS41262D-page 90 © 2007 Microchip Technology Inc. ...

Page 93

... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2007 Microchip Technology Inc. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘ ...

Page 94

... Holding Register for the 8-bit TMR2 Register T2CON — TOUTPS3 TOUTPS2 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: PIC16F685/PIC16F690 only. DS41262D-page 92 (1) R/W-0 R/W-0 TOUTPS1 TOUTPS0 TMR2ON U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 95

... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN © 2007 Microchip Technology Inc. FIGURE 8-1: SINGLE COMPARATOR – ...

Page 96

... Q1 is held high during Sleep mode. C1POL To Data Bus RD_CM1CON0 Set C1IF other peripherals C1OUT (to SR latch) ). OSC C2POL To Data Bus RD_CM2CON0 Set C2IF SYNCC2OUT MUX to Timer1 Gate, SR latch 1 and other peripherals ). OSC © 2007 Microchip Technology Inc. ...

Page 97

... Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 8.9 “Comparator SR Latch” for more information on the Internal Voltage Reference module. © 2007 Microchip Technology Inc. 8.2.4 COMPARATOR OUTPUT SELECTION control ...

Page 98

... Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before comparator interrupts. © 2007 Microchip Technology Inc. reset by software enabling ...

Page 99

... INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states. © 2007 Microchip Technology Inc. DS41262D-page 97 ...

Page 100

... Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding PORT TRIS bit = 0. DS41262D-page 98 R/W-0 U-0 C1POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > C1V - < C1V - > C1V - < C1V - IN IN (1) output REF R/W-0 R/W-0 R/W-0 C1R C1CH1 C1CH0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 101

... C2 connects to C12IN2- pin C2V - of C2 connects to C12IN3- pin IN Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding PORT TRIS bit = 0. © 2007 Microchip Technology Inc. R/W-0 U-0 C2POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > C2V ...

Page 102

... The analog SS 2: Analog levels on any pin defined as a and the DD digital input, may cause the input buffer to consume more current than is specified ≈ 0. LEAKAGE ≈ 0. ±500 nA Vss IC To ADC Input © 2007 Microchip Technology Inc. ...

Page 103

... Output is synchronous to falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-3. © 2007 Microchip Technology Inc. 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register. When enabled, the C2 output is latched on the falling edge of the Timer1 clock source ...

Page 104

... CMxCON0 registers must be set in order to make the comparator or latch outputs available on the output pins. The latch configuration enable states are completely independent of the enable states for the comparators. SR0 0 MUX (1) Latch MUX 0 SR1 © 2007 Microchip Technology Inc. C1OE (3) C1OUT pin C2OE (3) C2OUT pin ...

Page 105

... The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation enable an SR latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured. © 2007 Microchip Technology Inc. R/W-0 R/S-0 R/S-0 ...

Page 106

... The comparator voltage reference is V therefore, the The tested absolute accuracy of the Comparator DD Voltage Reference can be found in Section 17.0 “Electrical Specifications”. DD × /32 with no SS module current. REF derived and DD output changes with fluctuations in REF © 2007 Microchip Technology Inc. ...

Page 107

... CV REF To Comparators and ADC module C1VREN C2VREN FixedRef To Comparators and ADC module © 2007 Microchip Technology Inc. 8.10.7 VOLTAGE REFERENCE SELECTION , with DD Multiplexers on the output of the Voltage Reference module enable selection of either the CV voltage reference for use by the comparators. Setting the C1VREN bit of the VRCON register enables ...

Page 108

... RA0 --xx xxxx --uu uuuu RC0 xxxx xxxx uuuu uuuu — --00 000- --00 000- — 0000 00-- 0000 00-- TRISA0 --11 1111 --11 1111 TRISC0 1111 1111 1111 1111 VR0 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...

Page 109

... RB4/AN10/SDI/SDA RB5/AN11/RX/DT CV REF VP6 Reference Note 1: P1C and P1D available on PIC16F685/PIC16F690 only. 2: SS, SDO, SDA, RX and DT available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 3: ADC module applies to the PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 devices only. © 2007 Microchip Technology Inc. Figure 9-1 shows the block diagram of the ADC. (ADC) allows V DD ...

Page 110

... Section 17.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: Unless using the F , any changes in the RC system clock frequency will change the ADC clock frequency, adversely affect the ADC result. © 2007 Microchip Technology Inc. periods AD specification AD which may ...

Page 111

... Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the interrupt service routine. Please see Section 9.1.5 “Interrupts” for more information. © 2007 Microchip Technology Inc DEVICE OPERATING FREQUENCIES ( Device Frequency (F ...

Page 112

... Figure 9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ DS41262D-page 110 ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 © 2007 Microchip Technology Inc. ...

Page 113

... SLEEP instruction causes the present conver- RC sion to be aborted and the ADC module is turned off, although the ADON bit remains set. © 2007 Microchip Technology Inc. 9.2.5 SPECIAL EVENT TRIGGER An ECCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero ...

Page 114

... ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. DS41262D-page 112 © 2007 Microchip Technology Inc. ...

Page 115

... A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘ ...

Page 116

... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ DS41262D-page 114 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 117

... ADRES5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2007 Microchip Technology Inc. R/W-x R/W-x R/W-x ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x ...

Page 118

... SS S Ω Ω 10k ln(0.0004885 0.05µ 50°C- 25°C /° has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD Ω 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED © 2007 Microchip Technology Inc. ...

Page 119

... SS = Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h 003h 002h 001h 000h REF © 2007 Microchip Technology Inc Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 ...

Page 120

... TMR1IE -000 0000 -000 0000 TMR1IF -000 0000 -000 0000 RA0 --xx xxxx --uu uuuu — xxxx ---- uuuu ---- RC0 xxxx xxxx uuuu uuuu TRISA0 --11 1111 --11 1111 — 1111 ---- 1111 ---- TRISC0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...

Page 121

... DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL Data EEPROM memory is readable and writable and the Flash program memory (PIC16F685/PIC16F689/ PIC16F690 only) is readable during normal operation (full V range). These memories are not directly DD mapped in the register file space. Instead, they are indi- rectly addressed through the Special Function Regis- ters (SFRs) ...

Page 122

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 EEADRH<3:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads Note 1: PIC16F685/PIC16F689/PIC16F690 only. DS41262D-page 120 R/W-0 R/W-0 R/W-0 EEDAT4 EEDAT3 EEDAT2 U = Unimplemented bit, read as ‘0’ ...

Page 123

... Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read Note 1: PIC16F685/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc. U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘ ...

Page 124

... WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. © 2007 Microchip Technology Inc. ...

Page 125

... PIC16F631/677/685/687/689/690 10.1.4 READING THE FLASH PROGRAM MEMORY (PIC16F685/PIC16F689/ PIC16F690) To read a program memory location, the user must write the Least and Most Significant address bits to the EEADR and EEADRH registers, set the EEPGD con- trol bit of the EECON1 register, and then set control bit RD ...

Page 126

... BSF EECON1,RD executed here executed here RD bit EEDATH EEDAT Register EERHLT DS41262D-page 124 EEADRH,EEADR PC+3 INSTR ( EEDATH,EEDAT INSTR ( INSTR( Forced NOP executed here executed here INSTR ( INSTR( INSTR( executed here executed here © 2007 Microchip Technology Inc. ...

Page 127

... Data memory can be code-protected by programming the CPD bit in the Configuration Word register (Register 14-1) to ‘0’. © 2007 Microchip Technology Inc. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory ...

Page 128

... C1IE PIR2 OSFIF C2IF C1IF Legend unknown unchanged, — = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: PIC16F685/PIC16F689/PIC16F690 only. 2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. DS41262D-page 126 Bit 4 Bit 3 Bit 2 Bit 1 — WRERR WREN WR EEADR4 EEADR3 ...

Page 129

... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. Table 11-1 shows the timer resources required by the ECCP module. ...

Page 130

... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2007 Microchip Technology Inc. ...

Page 131

... Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the port I/O data latch. © 2007 Microchip Technology Inc. 11.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...

Page 132

... In PWM mode, CCPR1H is a read-only register. DS41262D-page 130 The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 11-4: Period Pulse Width TMR2 = 0 CCP1 TRIS ), or OSC CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> © 2007 Microchip Technology Inc. ...

Page 133

... PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2007 Microchip Technology Inc. EQUATION 11-2: Pulse Width EQUATION 11-3: • OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation ...

Page 134

... T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clearing the associated TRIS bit. DS41262D-page 132 © 2007 Microchip Technology Inc. ...

Page 135

... Full-Bridge, Reverse 11 Note 1: Pulse Steering enables outputs in Single mode. © 2007 Microchip Technology Inc. The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. ...

Page 136

... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). DS41262D-page 134 Pulse 0 Width Period (1) (1) Delay Delay © 2007 Microchip Technology Inc. PR2+1 ...

Page 137

... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). © 2007 Microchip Technology Inc. Pulse 0 Width Period (1) (1) Delay Delay PR2+1 ...

Page 138

... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...

Page 139

... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 11-10: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2007 Microchip Technology Inc FET Driver Load FET Driver QB V- ...

Page 140

... EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41262D-page 138 Period (1) Period (1) © 2007 Microchip Technology Inc. ...

Page 141

... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2007 Microchip Technology Inc. The Full-Bridge mode does not provide dead-band delay ...

Page 142

... The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41262D-page 140 Forward Period Reverse Period OFF – T OFF ON © 2007 Microchip Technology Inc. ...

Page 143

... Pins P1B and P1D tri-state Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1. © 2007 Microchip Technology Inc. A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘ ...

Page 144

... PWM Activity Start of PWM Period DS41262D-page 142 is a condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears ECCPASE Cleared by Firmware PWM Resumes PWM Resumes © 2007 Microchip Technology Inc. ...

Page 145

... See Figure 11-8 for illustration. The lower seven bits of the associated PWM1CON register (Register 11-3) sets the delay period in terms of microcontroller instruction cycles (T CY FIGURE 11-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) © 2007 Microchip Technology Inc. FIGURE 11-16: Pulse Width (2) P1A td (2) P1B ...

Page 146

... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. DS41262D-page 144 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles between the scheduled time when a PWM signal OSC OSC R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 147

... P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> and P1M<1:0> = 00. © 2007 Microchip Technology Inc. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. ...

Page 148

... TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. DS41262D-page 146 P1A pin P1B pin P1C pin P1D pin © 2007 Microchip Technology Inc. ...

Page 149

... PORT Data FIGURE 11-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data © 2007 Microchip Technology Inc. Figures 11-19 and 11-20 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. PORT Data P1n = PWM P1n = PWM PORT Data DS41262D-page 147 ...

Page 150

... TMR1IE -000 0000 -000 0000 TMR1IF -000 0000 -000 0000 STRA ---0 0001 ---0 0001 PDC0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...

Page 151

... SPBRGH SPBRG BRGH BRG16 © 2007 Microchip Technology Inc. The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...

Page 152

... OSC ÷ x16 x64 FERR Register 12-1, CREN OERR RCIDL RSR Register LSb • • • ( Start RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2007 Microchip Technology Inc. ...

Page 153

... TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. © 2007 Microchip Technology Inc. Note 1: When the SPEN bit is set, the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the EUSART receiver is enabled ...

Page 154

... TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. © 2007 Microchip Technology Inc. ...

Page 155

... TRISB6 TRISB5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2007 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE RABIE ...

Page 156

... PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. Receiving Data Receive Interrupts © 2007 Microchip Technology Inc. ...

Page 157

... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2007 Microchip Technology Inc. 12.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...

Page 158

... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Start bit Stop bit 7/8 bit © 2007 Microchip Technology Inc. ...

Page 159

... TRISB6 TRISB5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2007 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE RABIE ...

Page 160

... Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) feature (see Section 12.3.1 R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 161

... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...

Page 162

... Auto-Baud Detect mode is enabled (clears when auto-baud is complete Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41262D-page 160 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 163

... TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. © 2007 Microchip Technology Inc. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...

Page 164

... F = 8.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — — — — — — — — 2404 0.16 207 — 71 9615 0. 10417 0. 19231 0. 55556 -3. — — — © 2007 Microchip Technology Inc. ...

Page 165

... Microchip Technology Inc. SYNC = 0, BRGH = 1, BRG16 = 3.6864 MHz F = 2.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — — — ...

Page 166

... F = 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) 1666 300.1 0.04 832 416 1202 0.16 207 207 2404 0.16 103 51 9615 0. 10417 0. 19.23k 0. — — — — — — — © 2007 Microchip Technology Inc. ...

Page 167

... SPBRGH Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. © 2007 Microchip Technology Inc. and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. ...

Page 168

... WUE bit receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Cleared due to User Read of RCREG © 2007 Microchip Technology Inc. Auto Cleared ...

Page 169

... Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. © 2007 Microchip Technology Inc Q1Q2 Q3 Q4 Cleared due to User Read of RCREG Sleep Ends 12 ...

Page 170

... BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB SENDB (send Break control bit) DS41262D-page 168 bit 0 bit 1 bit 11 Break Sampled Here Stop bit Auto Cleared © 2007 Microchip Technology Inc. ...

Page 171

... A clock polarity option is provided for Microwire compatability. Clock polarity is selected with the SCKP bit of the BAUDCTL register. Setting the SCKP bit sets © 2007 Microchip Technology Inc. the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. ...

Page 172

... TMR1IF -000 0000 -000 0000 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 1111 ---- 1111 ---- 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2007 Microchip Technology Inc. ...

Page 173

... Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2007 Microchip Technology Inc. 12.4.1.8 Synchronous Master Reception Set-up: 1. ...

Page 174

... TMR1IF -000 0000 -000 0000 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 1111 ---- 1111 ---- 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2007 Microchip Technology Inc. ...

Page 175

... TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2007 Microchip Technology Inc. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...

Page 176

... TMR1IF -000 0000 -000 0000 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 1111 ---- 1111 ---- 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2007 Microchip Technology Inc. ...

Page 177

... PORTC). If read-write-modify instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<7> bit to be set, thus disabling the SDO output. © 2007 Microchip Technology Inc. FIGURE 13-1: Read SDI/SDA SDO Peripheral OE SS Control ...

Page 178

... Receive (SPI and I C modes Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty 2 Transmit (I C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Note 1: PIC16F687/PIC16F689/PIC16F690 only. DS41262D-page 176 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 ...

Page 179

... C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: PIC16F687/PIC16F689/PIC16F690 only. 2: When this mode is selected, any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register. © 2007 Microchip Technology Inc. (1) ...

Page 180

... Example 13-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSP Status register (SSPSTAT) indicates the various status conditions. © 2007 Microchip Technology Inc. ...

Page 181

... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb Processor 1 © 2007 Microchip Technology Inc. 13.4 Typical Connection Figure 13-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...

Page 182

... T OSC • F /64 (or 16 • T OSC • Timer2 output/2 (PIC16F685/PIC16F690 only) This allows a maximum data rate (at 40 MHz Mbps. Figure 13-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit ...

Page 183

... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = ...

Page 184

... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41262D-page 182 bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...

Page 185

... CKE Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. Note 1: PIC16F687/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc. 13.10 Bus Mode Compatibility Table 13-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...

Page 186

... For high and low times of the I specification, as well as the requirements of the SSP module, see Section 17.0 “Electrical Specifications” modes to be selected mode with the SSPEN bit set 2 C module. is received, the hardware 2 C © 2007 Microchip Technology Inc. ...

Page 187

... Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. © 2007 Microchip Technology Inc. The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. Receive first (high) byte of address (bits SSPIF, BF and bit UA (SSPSTAT< ...

Page 188

... Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. Receiving Data ACK Bus Master terminates transfer ACK is not sent. © 2007 Microchip Technology Inc. ...

Page 189

... SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing the SSPMSK register all other SSP modes, this bit has no effect. © 2007 Microchip Technology Inc. This register must be initiated prior to setting SSPM<3:0> bits to select the I ...

Page 190

... PIC16F631/677/685/687/689/690 2 FIGURE 13-9: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) DS41262D-page 188 © 2007 Microchip Technology Inc. ...

Page 191

... SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) © 2007 Microchip Technology Inc. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse ...

Page 192

... PIC16F631/677/685/687/689/690 2 I FIGURE 13-11: C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS41262D-page 190 © 2007 Microchip Technology Inc. ...

Page 193

... Slave mode idle (SSPM<3:0> = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. © 2007 Microchip Technology Inc. 13.14 Multi-Master Mode In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions, allows the determination of when the bus is free ...

Page 194

... ADIE Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the SSP module. Note 1: PIC16F687/PIC16F689/PIC16F690 only. 2: SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001. See Registers 13-2 and 13-3 for more details. 3: Maintain these bits clear. ...

Page 195

... Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 14-2). © 2007 Microchip Technology Inc. DS41262D-page 193 ...

Page 196

... Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h- 3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Programming (DS41204) for more information. DS41262D-page 194 Specification” © 2007 Microchip Technology Inc. ...

Page 197

... The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. © 2007 Microchip Technology Inc. FCMEN IESO BOREN1 PWRTE ...

Page 198

... A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 14-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 17.0 “Electrical Specifications” for pulse-width specifications Enable PWRT Enable OST © 2007 Microchip Technology Inc. Chip_Reset Q ...

Page 199

... MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull- © 2007 Microchip Technology Inc. FIGURE 14- kΩ ...

Page 200

... Brown-out Reset Word and the Power-up Timer will be re-initialized. Once V rises above V , the Power-up Timer will execute a BOR 64 ms Reset. ( & rises DD while the Power-up Timer BOR V BOR V BOR © 2007 Microchip Technology Inc. ...

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