PIC16F73 Microchip Technology Inc., PIC16F73 Datasheet

no-image

PIC16F73

Manufacturer Part Number
PIC16F73
Description
Manufacturer
Microchip Technology Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F73
Manufacturer:
JST
Quantity:
1 818
Part Number:
PIC16F73-1/SP
Manufacturer:
AMD
Quantity:
302
Part Number:
PIC16F73-1/SP4AP
Manufacturer:
a
Quantity:
1 200
Part Number:
PIC16F73-E/SS
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC16F73-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC16F73-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC16F73-I/SO
0
Company:
Part Number:
PIC16F73-I/SO
Quantity:
5 000
Part Number:
PIC16F73-I/SP
Manufacturer:
MICROCHIP
Quantity:
10 000
Part Number:
PIC16F73-I/SP
Manufacturer:
MICROCH
Quantity:
2 142
Part Number:
PIC16F73-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC16F73-I/SP
0
Company:
Part Number:
PIC16F73-I/SP
Quantity:
5 000
Part Number:
PIC16F73-I/SS
Manufacturer:
MICROCHIP
Quantity:
48
Part Number:
PIC16F73-I/SS
Manufacturer:
MICROCHIP
Quantity:
5
Part Number:
PIC16F73-I/SS
Manufacturer:
MICRO/PBF
Quantity:
31
M
PIC16F7X
Data Sheet
28/40-pin, 8-bit CMOS FLASH
Microcontrollers
 2002 Microchip Technology Inc.
DS30325B

Related parts for PIC16F73

PIC16F73 Summary of contents

Page 1

... Microchip Technology Inc. M 28/40-pin, 8-bit CMOS FLASH PIC16F7X Data Sheet Microcontrollers DS30325B ...

Page 2

... QS-9000 compliant for its PICmicro ® 8-bit MCUs ® code hopping EE OQ devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc. ...

Page 3

... M 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F73 • PIC16F76 • PIC16F74 • PIC16F77 High Performance RISC CPU: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two-cycle • ...

Page 4

... RB3/PGM 23 RB2 22 RB1 21 RB0/INT RC7/RX/DT RC6/TX/CK 17 RC5/SDO 16 RC4/SDI/SDA 15 MLF RA2/AN2 1 RA3/AN3/V REF 2 RA4/T0CKI PIC16F73 3 RA5/AN4/SS 4 PIC16F76 OSC1/CLKI 6 7 OSC2/CLKO RB7/PGD 39 RB6/PGC 38 RB5 37 RB4 RB3/PGM 36 RB2 35 34 RB1 33 RB0/INT ...

Page 5

... RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC QFP RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RB0/INT RB1 RB2 RB3/PGM  2002 Microchip Technology Inc. 39 RB3/PGM 7 38 RB2 8 37 RB1 9 36 RB0/INT 10 PIC16F77 PIC16F74 33 RD7/PSP7 ...

Page 6

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30325B-page 4  2002 Microchip Technology Inc. ...

Page 7

... PIC16F73 • PIC16F74 • PIC16F76 • PIC16F77 PIC16F73/76 devices are available only in 28-pin pack- ages, while PIC16F74/77 devices are available in 40-pin and 44-pin packages. All devices in the PIC16F7X family share common architecture, with the following differences: • ...

Page 8

... PIC16F7X FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM 13 FLASH Program Memory Program 14 Bus Instruction reg 8 Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Timer0 Timer1 CCP1 CCP2 Device PIC16F73 PIC16F76 Note 1: Higher order bits are from the STATUS register. DS30325B-page 6 8 Data Bus ...

Page 9

... Timing Generation OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 Timer1 CCP1 CCP2 Device PIC16F74 PIC16F77 Note 1: Higher order bits are from the STATUS register.  2002 Microchip Technology Inc. 8 Data Bus Program Counter RAM 8 Level Stack File (13-bit) Registers (1) RAM Addr 9 Addr MUX Indirect ...

Page 10

... PIC16F7X TABLE 1-2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION DIP SSOP MLF Pin Name SOIC Pin# Pin# OSC1/CLKI 9 6 OSC1 CLKI OSC2/CLKO 10 7 OSC2 CLKO MCLR MCLR V PP RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2 4 1 RA2 AN2 RA3/AN3 REF ...

Page 11

... TABLE 1-2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION (CONTINUED) DIP SSOP MLF Pin Name SOIC Pin# Pin# RB0/INT 21 18 RB0 INT RB1 22 19 RB2 23 20 RB3/PGM 24 21 RB3 PGM RB4 25 22 RB5 26 23 RB6/PGC 27 24 RB6 PGC RB7/PGD 28 25 RB7 PGD RC0/T1OSO/T1CKI 11 8 RC0 ...

Page 12

... Digital I/O. I Analog input 2. TTL I/O Digital I/O. I Analog input 3. I A/D reference voltage input. ST I/O Digital I/O – Open drain when configured as output. I Timer0 external clock input. TTL I/O Digital I/O. I SPI slave select input. I Analog input 4. I/O = input/output P = power ST = Schmitt Trigger input Description  2002 Microchip Technology Inc. ...

Page 13

... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2002 Microchip Technology Inc. I/O/P Buffer Type Type PORTB is a bi-directional I/O port ...

Page 14

... Chip select control for parallel slave port . I Analog input 7. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. — These pins are not internally connected. These pins should be left unconnected. I/O = input/output ST = Schmitt Trigger input Description P = power  2002 Microchip Technology Inc. ...

Page 15

... The PIC16F77/76 devices have 8K words of FLASH program memory and the PIC16F73/74 devices have 4K words. The program memory maps for PIC16F7X devices are shown in Figure 2-1. Accessing a location above the physically implemented address will cause a wraparound. ...

Page 16

... Purpose 118h 198h Register 119h 16 Bytes 199h 11Ah 19Ah 11Bh 19Bh 11Ch 19Ch 11Dh 19Dh 11Eh 19Eh 11Fh 19Fh 120h 1A0h General Purpose Register 80 Bytes 1EFh 16Fh 1F0h 170h accesses 70h - 7Fh 17Fh 1FFh Bank 3  2002 Microchip Technology Inc. ...

Page 17

... General Purpose Register 96 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ’0’. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices.  2002 Microchip Technology Inc. File Address Indirect addr.(*) 80h TMR0 81h PCL PCL 82h STATUS ...

Page 18

... CCP1M1 CCP1M0 54, 96 --00 0000 OERR RX9D 70, 96 0000 -00x 74, 96 0000 0000 76, 96 0000 0000 58, 96 xxxx xxxx 58, 96 xxxx xxxx CCP2M1 CCP2M0 54, 96 --00 0000 88, 96 xxxx xxxx — ADON 83, 96 0000 00-0  2002 Microchip Technology Inc. ...

Page 19

... Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: This bit always reads as a ‘1’.  2002 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...

Page 20

... DC C 19, 96 0001 1xxx 27, 96 xxxx xxxx — — 34, 96 1111 1111 — — — — — — 21, 96 ---0 0000 INTF RBIF 23, 96 0000 000x — RD 29, 97 1--- ---0 — 0000 0000 0000 0000  2002 Microchip Technology Inc. ...

Page 21

... Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). ...

Page 22

... W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 23

... At least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 24

... DS30325B-page 22 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 25

... TMR1 register did not overflow Note 1: PSPIF is reserved on 28-pin devices; always maintain this bit clear. Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 26

... U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 U-0 R/W-0 — — CCP2IE bit Bit is unknown U-0 U-0 R/W-0 — — CCP2IF bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 27

... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred ...

Page 28

... ORG SUB1_P1 : : : RETURN contents of the PCLATH are CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 0x500 PCLATH,4 PCLATH,3 ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) 0x900 ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to Call ;subroutine in page 0 ;(000h-7FFh)  2002 Microchip Technology Inc. ...

Page 29

... DIRECT/INDIRECT ADDRESSING Direct Addressing From Opcode RP1:RP0 6 Bank Select Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-2.  2002 Microchip Technology Inc. EXAMPLE 2-2: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE : 0 IRP Bank Select ...

Page 30

... PIC16F7X NOTES: DS30325B-page 28  2002 Microchip Technology Inc. ...

Page 31

... Initiates a FLASH read cleared in hardware. The RD bit can only be set (not cleared) in software FLASH read completed Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. When interfacing to the program memory block, the PMDATH:PMDATA registers form a two-byte word, which holds PMADRH:PMADR registers form a two-byte word, which holds the 13-bit address of the FLASH location being accessed ...

Page 32

... Address Register High Byte Data Register High Byte — — — — Value on: Value on Bit 0 POR, all other BOR RESETS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — RD 1--- ---0 1--- ---0  2002 Microchip Technology Inc. ...

Page 33

... Configure all pins MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6>are always ; read as ’0’.  2002 Microchip Technology Inc. FIGURE 4-1: Data Bus Port CK Q Manual, Data Latch TRIS Q CK ...

Page 34

... Input/output or slave select input for synchronous serial port or analog input. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 PORTA Data Direction Register — — — PCFG2 PCFG1 PCFG0 Value on: Value on all Bit 0 POR, other BOR RESETS RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -000 ---- -000  2002 Microchip Technology Inc. ...

Page 35

... PORTB. The “mismatch” outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).  2002 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the ...

Page 36

... Bit 2 RB6 RB5 RB4 RB3 RB2 INTEDG T0CS T0SE PSA PS2 Value on: Value on Bit 1 Bit 0 POR, all other BOR RESETS RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS1 PS0 1111 1111 1111 1111  2002 Microchip Technology Inc. ...

Page 37

... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC RC7 RC6 87h TRISC PORTC Data Direction Register Legend unknown unchanged  2002 Microchip Technology Inc. FIGURE 4-5: Port/Peripheral Select Peripheral Data Out Data Bus D WR Port Data Latch D WR TRIS TRIS Latch RD TRIS Peripheral ...

Page 38

... PIC16F7X 4.4 PORTD and TRISD Registers This section is not applicable to the PIC16F73 or PIC16F76. PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configureable as an input or output. PORTD can be configured as an 8-bit wide micro- processor port (parallel slave port) by setting control bit PSPMODE (TRISE< ...

Page 39

... PORTE and TRISE Register This section is not applicable to the PIC16F73 or PIC16F76. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the micro- processor port when bit PSPMODE (TRISE< ...

Page 40

... Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend Readable bit - n = Value at POR reset DS30325B-page 38 R-0 R/W-0 R/W-0 OBF IBOV PSPMODE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 R/W-1 R/W-1 R/W-1 — Bit2 Bit1 Bit0 bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 41

... IBOV 9Fh ADCON1 — — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTE.  2002 Microchip Technology Inc. Function (1) Input/output port pin or read control input in Parallel Slave Port mode or analog input. For RD (PSP mode IDLE 0 = Read operation. Contents of PORTD register output to PORTD I/O pins (if chip selected) ...

Page 42

... PIC16F7X 4.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F73 or PIC16F76. PORTD operates as an 8-bit wide Parallel Slave Port, or Microprocessor Port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode asynchronously readable and writable by an external system using the ...

Page 43

... PSPIE 9Fh ADCON1 — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.  2002 Microchip Technology Inc ...

Page 44

... PIC16F7X NOTES: DS30325B-page 42  2002 Microchip Technology Inc. ...

Page 45

... Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  2002 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by ...

Page 46

... R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA WDT Rate 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 47

... OPTION_REG RBPU INTEDG Legend unknown unchanged unimplemented locations read as ’0’. Shaded cells are not used by Timer0.  2002 Microchip Technology Inc. however, these lines must be used to set a temporary value. The final 1:1 value is then set in lines 10 and 11 (highlighted). (Line numbers are included in the exam- ple for illustrative purposes only, and are not part of the actual code ...

Page 48

... PIC16F7X NOTES: DS30325B-page 46  2002 Microchip Technology Inc. ...

Page 49

... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). ...

Page 50

... T1OSC RC0/T1OSO/T1CKI (2) RC1/T1OSI/CCP2 Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. 2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode. DS30325B-page 48 6.2 Timer1 Counter Operation Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit. ...

Page 51

... TMR1L Read low byte MOVWF TMPL ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code  2002 Microchip Technology Inc. PIC16F7X 6.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware) ...

Page 52

... T1CON — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. DS30325B-page 50 TABLE 6-1: Osc Type LP Capacitor values are for design guidance only. ...

Page 53

... Register 7-1 shows the Timer2 control register. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).  2002 Microchip Technology Inc. 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • ...

Page 54

... T2CON — 92h PR2 Timer2 Period Register Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. DS30325B-page 52 R/W-0 R/W-0 R/W-0 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 55

... The rising edges are aligned. PWM Capture None. PWM Compare None.  2002 Microchip Technology Inc. PIC16F7X 8.2 CCP2 Module Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match ...

Page 56

... PWM mode Legend Readable bit - n = Value at POR reset DS30325B-page 54 U-0 R/W-0 R/W-0 R/W-0 — CCPxX CCPxY CCPxM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit Bit is unknown  2002 Microchip Technology Inc. ...

Page 57

... The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.  2002 Microchip Technology Inc. 8.3.4 CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0 ...

Page 58

... CCP2CON — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear. DS30325B-page 56 8.4.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. ...

Page 59

... RESET RESET Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2  2002 Microchip Technology Inc. 8.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = PWM frequency is defined [PWM period]. ...

Page 60

... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. DS30325B-page 58 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. ...

Page 61

... Module in the I C Multi-Master (DS00578).  2002 Microchip Technology Inc. 9.2 SPI Mode This section contains register definitions and opera- tional characteristics of the SPI module. Additional information on the SPI module can be found in the PICmicro™ Mid-Range MCU Family Reference Man- ual (DS33023A). ...

Page 62

... C mode only) C mode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-0 R bit 0 ® ) ® alternate) ® default Bit is unknown  2002 Microchip Technology Inc. ...

Page 63

... I C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ® ...

Page 64

... TRISC<5> bit (see Section 4.3 for infor- mation on PORTC). If Read-Modify-Write instructions, such as BSF are performed on the TRISC register while the SS pin is high, this will cause the TRISC<5> bit to be set, thus disabling the SDO output  2002 Microchip Technology Inc. ...

Page 65

... SDI (SMP = 0) bit7 SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 SDI (SMP = 0) bit7 SSPIF  2002 Microchip Technology Inc. bit6 bit5 bit4 bit3 bit6 bit5 bit3 bit4 bit5 bit3 bit2 bit4 PIC16F7X ...

Page 66

... SSPSTAT SMP CKE Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. DS30325B-page 64 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 67

... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD)  2002 Microchip Technology Inc. The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...

Page 68

... An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the byte. Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes  2002 Microchip Technology Inc. ...

Page 69

... FIGURE 9- WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL Data in sampled SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>)  2002 Microchip Technology Inc. Receiving Data ACK ACK ...

Page 70

... TRISC PORTC Data Direction Register Legend unknown unchanged unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear Maintain these bits clear mode. ...

Page 71

... TX9D: 9th bit of Transmit Data Can be parity bit Legend Readable bit - n = Value at POR reset  2002 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to ...

Page 72

... Can be parity bit (parity to be calculated by firmware) Legend Readable bit - n = Value at POR reset DS30325B-page 70 R/W-0 R/W-0 U-0 R-0 SREN CREN — FERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared  2002 Microchip Technology Inc. R-0 R-x OERR RX9D bit Bit is unknown ...

Page 73

... RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used by the BRG.  2002 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the F OSC baud rate error in some cases ...

Page 74

... VALUE ERROR (DECIMAL) 301 0.23% 185 -0.83% 46 1.32% 22 -2.90% 5 -2.90% 2 -27.17% 1 -2.90% 0 — — — MHz OSC SPBRG % VALUE ERROR (DECIMAL) 1.73% 255 0.16% 64 -1.36% 32 1.73% 15 -1.36% 10 1.73% 7 -6.99% 6 8.51% 4 -16.67% 2 4.17 3.579545 MHz OSC SPBRG % VALUE ERROR (DECIMAL) 0.23% 185 0.23% 92 1.32% 22 -2.90% 11 -2.90% 5 -2.90% 3 -2.90% 2 16.52% 1 -2.90% 1 -10.51% 0  2002 Microchip Technology Inc. ...

Page 75

... TXEN Baud Rate CLK SPBRG Baud Rate Generator  2002 Microchip Technology Inc. are set. The TXIF interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register ...

Page 76

... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. DS30325B-page 74 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF ...

Page 77

... RC7/RX/DT Pin Buffer and Control SPEN  2002 Microchip Technology Inc. is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA< ...

Page 78

... TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear. DS30325B-page 76 START bit7/8 STOP bit7/8 ...

Page 79

... TSR register is empty transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.  2002 Microchip Technology Inc. PIC16F7X Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter ...

Page 80

... Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear. DS30325B-page 78 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 ...

Page 81

... RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRG = ’0’.  2002 Microchip Technology Inc. receive data. Reading the RCREG register will load bit RX9D with a new value, therefore essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information ...

Page 82

... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear. 10.4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master ...

Page 83

... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.  2002 Microchip Technology Inc. Bit 5 Bit 4 ...

Page 84

... PIC16F7X NOTES: DS30325B-page 82  2002 Microchip Technology Inc. ...

Page 85

... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The 8-bit analog-to-digital (A/D) converter module has five inputs for the PIC16F73/76 and eight for the PIC16F74/77. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number. The output of the sample and hold is the input into the converter, which generates the result via successive approximation ...

Page 86

... Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 (1) (1) (1) RE0 RE1 RE2 V REF RA3 RA3 RA3 Bit is unknown  2002 Microchip Technology Inc. ...

Page 87

... Set GIE bit 3. Select an A/D input channel (ADCON0). FIGURE 11-1: A/D BLOCK DIAGRAM A/D Converter V REF (Reference Voltage) Note 1: Not available on PIC16F73/76.  2002 Microchip Technology Inc. 4. Wait for at least an appropriate acquisition period. 5. Start conversion: • Set GO/DONE bit (ADCON0) 6. Wait for the A/D conversion to complete, by either: • ...

Page 88

... AD , see ACQ will be no more than 16 µsec HOLD = DAC Capacitance = 51 Sampling Switch (k Ω ) Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz (Note 1)  2002 Microchip Technology Inc. ...

Page 89

... SLEEP whenever ADIF is set by hardware. In addition, an interrupt will also occur if the global interrupt bit GIE (INTCON<7>) is set.  2002 Microchip Technology Inc. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be changed, and the ADIF flag will not be set ...

Page 90

... IBF OBF Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. 2: These registers are reserved on the PIC16F73/76. DS30325B-page 88 with minimal software overhead (moving the ADRES to the desired location) ...

Page 91

... RESET while the power supply stabilizes, and is enabled or disabled, using a configuration bit. With these two timers on-chip, most applications need no external RESET circuitry.  2002 Microchip Technology Inc. PIC16F7X SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt ...

Page 92

... Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. Legend Readable bit P = Programmable bit - n = Value when device is unprogrammed DS30325B-page 90 (1) U-0 U-0 R/P-1 U-0 R/P-1 — — BOREN — CP0 PWRTEN WDTEN FOSC1 FOSC0 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state R/P-1 R/P-1 R/P-1 R/P-1 bit0  2002 Microchip Technology Inc. ...

Page 93

... C2 Note 1: See Table 12-1 and Table 12-2 for recom- mended values of C1 and C2 series resistor (RS) may be required for AT strip cut crystals varies with the crystal chosen.  2002 Microchip Technology Inc. FIGURE 12-2: Clock from Ext. System TABLE 12-1: The Typical Capacitor Values Used: ...

Page 94

... PIC16F7X FIGURE 12- EXT C EXT OSC Recommended values: ) values, and the operat- EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC16F7X OSC2/CLKOUT / Ω ≤ R ≤ 100 k Ω EXT C > 20pF EXT  2002 Microchip Technology Inc. ...

Page 95

... Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.  2002 Microchip Technology Inc. PIC16F7X Some registers are not affected in any RESET condi- tion. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “ ...

Page 96

... RESET conditions for all the registers. to rise to an accept parameter #33). PWRT falls below V DD BOR BOR falls below V for less DD BOR rises above V . The DD BOR should fall DD , the Brown-out Reset pro- PWRT rises above V , with the DD BOR  2002 Microchip Technology Inc. ...

Page 97

... Legend unchanged unknown unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  2002 Microchip Technology Inc. if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable ...

Page 98

... Microchip Technology Inc. ...

Page 99

... See Table 12-5 for RESET value for specific condition. FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET  2002 Microchip Technology Inc. Power-on Reset, MCLR Reset, Brown-out Reset WDT Reset 77 ---- ---0 ---- ---0 77 ---- --qq ---- --uu ...

Page 100

... OST TIME-OUT INTERNAL RESET FIGURE 12-9: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30325B-page 98 T PWRT T PWRT THROUGH RC NETWORK PWRT T OST ): CASE OST ): CASE OST  2002 Microchip Technology Inc. ...

Page 101

... TMR1IE CCP2IF CCP2IE Note 1: PSP interrupt is implemented only on PIC16F74/77 devices.  2002 Microchip Technology Inc. PIC16F7X The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Spe- cial Function Registers, PIR1 and PIR2 ...

Page 102

... INTF TUS registers). This will have to be implemented in software, as shown in Example 12-1. For the PIC16F73/74 devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., If W_TEMP is defined at 20h in bank 0, it must also be defined at A0h in bank 1 ...

Page 103

... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits.  2002 Microchip Technology Inc. WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- ues for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register ...

Page 104

... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc- tion should be executed before a SLEEP instruction.  2002 Microchip Technology Inc. ...

Page 105

... This also allows the most recent firmware or a custom firmware to be pro- grammed.  2002 Microchip Technology Inc (2) T OST ...

Page 106

... PIC16F7X NOTES: DS30325B-page 104  2002 Microchip Technology Inc. ...

Page 107

... A read operation is performed on a register even if the instruction writes to that register.  2002 Microchip Technology Inc. PIC16F7X For example, a “clrf PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB ...

Page 108

... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk Mid-Range MCU ™  2002 Microchip Technology Inc. ...

Page 109

... Operation: Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'.  2002 Microchip Technology Inc. BCF k Syntax: Operands: Operation: Status Affected: Description: BSF Syntax: ...

Page 110

... DECF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ’f’. If ’d’ the result is stored in the W register. If ’d’ the result is stored back in register ’f’.  2002 Microchip Technology Inc. ...

Page 111

... Z Description: The contents of register ’f’ are incremented. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’.  2002 Microchip Technology Inc. PIC16F7X INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 ≤ f ≤ 127 Operands: d ∈ ...

Page 112

... Return with Literal label ] RETLW k 0 ≤ k ≤ 255 k → (W); TOS → PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.  2002 Microchip Technology Inc. ...

Page 113

... Carry Flag. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. C Register f  2002 Microchip Technology Inc. PIC16F7X SLEEP Syntax: [ label ] SLEEP Operands: None 00h → WDT, Operation: 0 → ...

Page 114

... Syntax: [ label ] XORWF 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (W) .XOR. (f) → (destination) Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'.  2002 Microchip Technology Inc. f,d ...

Page 115

... A project manager • Customizable toolbar and key mapping • A status bar • On-line help  2002 Microchip Technology Inc. The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...

Page 116

... PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.  2002 Microchip Technology Inc. ...

Page 117

... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.  2002 Microchip Technology Inc. 14.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...

Page 118

... Programming Tools K L evaluation and programming tools support EE OQ Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.  2002 Microchip Technology Inc. ...

Page 119

... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16C8X PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers  2002 Microchip Technology Inc. PIC16F7X Kits Eval and Boards Demo DS30325B-page 117 ...

Page 120

... PIC16F7X NOTES: DS30325B-page 118  2002 Microchip Technology Inc. ...

Page 121

... PORTD and PORTE are not implemented on the PIC16F73/76 devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied ...

Page 122

... PIC16LF7X VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (12 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10 MHz. MAX DS30325B-page 120 16 MHz Frequency 4 MHz 10 MHz Frequency - 2.5V MHz DDAPPMIN ® 20 MHz device in the application.  2002 Microchip Technology Inc. ...

Page 123

... DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) PIC16LF73/74/76/77 (Industrial) PIC16F73/74/76/77 (Industrial, Extended) Param Sym Characteristic No. V Supply Voltage DD D001 PIC16LF7X D001 PIC16F7X D001A D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to ensure ...

Page 124

... PIC16F7X 15.1 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) (Continued) PIC16LF73/74/76/77 (Industrial) PIC16F73/74/76/77 (Industrial, Extended) Param Sym Characteristic No. I Supply Current (Notes D010 PIC16LF7X D010A D010 PIC16F7X D013 ∆I D015* Brown-out BOR Reset Current (Note 6) D020 I Power-down Current (Notes PIC16LF7X D021 ...

Page 125

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2002 Microchip Technology Inc. PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature ...

Page 126

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30325B-page 124 PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature ...

Page 127

... Pin = 464 Ω for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16F73/76 devices.  2002 Microchip Technology Inc specifications only ...

Page 128

... LP osc mode ns XT osc mode ns HS osc mode ms LP osc mode ns RC osc mode ns XT osc mode ns HS osc mode ms LP osc mode 4/F CY OSC ns XT oscillator ms LP oscillator ns HS oscillator ns XT oscillator ns LP oscillator ns HS oscillator  2002 Microchip Technology Inc. ...

Page 129

... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output  2002 Microchip Technology Inc ...

Page 130

... V — 1024 T — — T OSC 28 72 132 ms V µ s — — 2.1 µ s 100 — — V  2002 Microchip Technology Inc. 34 Conditions = 5V, -40°C to +85° 5V, -40°C to +85° OSC1 period OSC = 5V, -40°C to +85°C DD ≤ V (D005) DD BOR ...

Page 131

... TCKEZtmr1 Delay from External Clock Edge to Timer Increment * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2002 Microchip Technology Inc ...

Page 132

... Extended(LF) — Standard(F) — Extended(LF) — Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1  2002 Microchip Technology Inc. ...

Page 133

... RD↑ or CS↓ to data out invalid * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2002 Microchip Technology Inc. 65 Characteristic Min Typ† Max Units 20 ...

Page 134

... SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 15-3 for load conditions. DS30325B-page 132 MSb Bit6 - - - - - -1 75, 76 Bit6 - - - - LSb Bit6 - - - - - -1 75, 76 Bit6 - - - -1 LSb LSb LSb  2002 Microchip Technology Inc. ...

Page 135

... FIGURE 15-14: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI MSb In 74 Note: Refer to Figure 15-3 for load conditions.  2002 Microchip Technology Inc MSb Bit6 - - - - - -1 75, 76 MSb In Bit6 - - - - Bit6 - - - - - -1 LSb 75, 76 Bit6 - - - -1 ...

Page 136

... STOP Condition  2002 Microchip Technology Inc. ...

Page 137

... I C BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 15-3 for load conditions.  2002 Microchip Technology Inc. Min Typ Max Units 100 kHz mode 4700 — — 400 kHz mode 600 — — 100 kHz mode 4000 — ...

Page 138

... After this period the first clock pulse is generated µs ns µs ns (Note 2) ns µs µs ns (Note 1) ns µs Time the bus must be free before a new transmission µs can start bus system, but the  2002 Microchip Technology Inc. ...

Page 139

... Data setup before CK↓ (DT setup time) 126 TckL2dtl Data hold after CK↓ (DT hold time) † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2002 Microchip Technology Inc. 121 Characteristic Min Standard(F) Extended(LF) ...

Page 140

... AIN REF ≤ V ≤ V — AIN REF V -40°C to +125°C V 0°C to +125°C V kΩ µA Average current consumption when A/D µ (Note 1). µA During V acquisition. AIN µA During A/D Conversion cycle.  2002 Microchip Technology Inc. ...

Page 141

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 11.1 for minimum conditions.  2002 Microchip Technology Inc. (1) 131 130 ...

Page 142

... PIC16F7X NOTES: DS30325B-page 140  2002 Microchip Technology Inc. ...

Page 143

... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) 6 Minimum: mean – 3 (-40°C to 125° 2002 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD 3 vs. F ...

Page 144

... MAXIMUM I DD 1.2 Typical: statistical mean @ 25°C 1.0 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 DS30325B-page 142 vs. F OVER V (XT MODE) OSC DD 1.5 2.0 2.5 F (MHz) OSC vs. F OVER V (XT MODE) OSC DD 1.5 2.0 2.5 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3.0 3.5 4.0 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3.0 3.5 4.0 2002 Microchip Technology Inc. ...

Page 145

... FIGURE 16-6: MAXIMUM I DD 100 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125° 2002 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (kHz) OSC vs. F OVER V ...

Page 146

... MODE pF 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 FIGURE 16-8: AVERAGE F OSC (RC MODE 100 pF 5.0 4.0 3.0 2.0 1.0 0.0 2.5 3.0 DS30325B-page 144 vs. V FOR VARIOUS VALUES Operation above 4 MHz is not recomended 3.5 4.0 4.5 V (V) DD vs. V FOR VARIOUS VALUES Operation above 4 MHz is not recomended 5 100 k 3.5 4.0 4 100 k 5.0 5.5 5.0 5.5 2002 Microchip Technology Inc. ...

Page 147

... MODE, ALL PERIPHERALS DISABLED 100 10 1 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 0.01 2.0 2.5 2002 Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.5 4.0 V (V) DD Max 125°C Max 85°C Typ 25°C 3.0 3 ...

Page 148

... Maximum: mean + 3 σ (-40°C to 125°C) Minimum: mean – 3 σ (-40°C to 125° 0.1 2.0 2.5 DS30325B-page 146 OVER TEMPERATURE Indeterminant State 3.0 3.5 4.0 V (V) DD vs. V OVER TEMPERATURE WDT DD Max (125˚C) Typ (25˚C) 3.0 3.5 4.0 V (V) DD Device in SLEEP Max (125˚C) Typ (25˚C) 4.5 5.0 5.5 4.5 5.0 5.5  2002 Microchip Technology Inc. ...

Page 149

... FIGURE 16-14: AVERAGE WDT PERIOD vs 125°C 35 85°C 30 25° -40° 2.0 2.5 2002 Microchip Technology Inc. (125°C) Typ (25°C) (-40°C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (- 125 C) DD 3.0 3.5 4.0 V (V) DD PIC16F7X (- 125 C) DD Typical: statistical mean @ 25°C Maximum: mean + 3 (-40° ...

Page 150

... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max Typ (25°C) Min (-mA 5V, - 125 C) DD Max Typ (25°C) Min 3V, - 125 2002 Microchip Technology Inc. ...

Page 151

... FIGURE 16-18: TYPICAL, MINIMUM AND MAXIMUM V 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.5 1.0 0.5 0 2002 Microchip Technology Inc. vs 5V, - 125 Typ (25°C) Min (-40° (-mA ...

Page 152

... INPUT, - 125 Max (-40° Typ (25° Min (125°C) TH 3.0 3.5 4.0 V (V) DD vs. V (ST INPUT, - 125 3.5 4.0 V (V) DD 4.5 5.0 5.5 Max (125°C) IH Min (-40° Max (-40° Min (125°C) IL 4.5 5.0 5.5 2002 Microchip Technology Inc. ...

Page 153

... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. PIC16F7X Example PIC16F77-I/SP 0210017 Example PIC16F76-I/SO 0210017 Example PIC16F73 -I/SS 0210017 Example 1 PIC16F73 -I/ML 0210017 DS30325B-page 151 ...

Page 154

... PIC16F7X Package Marking Information (Cont’d) 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30325B-page 152 Example PIC16F77-I/P 0210017 Example PIC16F77 -I/PT 0210017 Example PIC16F77 -I/L 0210017 2002 Microchip Technology Inc. ...

Page 155

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 2002 Microchip Technology Inc Units INCHES* MIN NOM ...

Page 156

... E .394 .407 .420 E1 .288 .295 .299 D .695 .704 .712 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. 2002 Microchip Technology Inc. ...

Page 157

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073 2002 Microchip Technology Inc Units ...

Page 158

... D .236 BSC D1 .226 BSC D2 .140 .146 .152 B .009 .011 .014 L .020 .024 .030 R .005 .007 .010 Q .012 .016 .026 CH .009 .017 .024 MILLIMETERS* MIN NOM MAX 28 0.65 BSC 0.85 1.00 0.65 0.80 0.00 0.01 0.05 0.20 REF. 6.00 BSC 5.75 BSC 3.55 3.70 3.85 6.00 BSC 5.75 BSC 3.55 3.70 3.85 0.23 0.28 0.35 0.50 0.60 0.75 0.13 0.17 0.23 0.30 0.40 0.65 0.24 0.42 0.60 12 2002 Microchip Technology Inc. ...

Page 159

... Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) (Continued SOLDER MASK Dimension Limits Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter Drawing No. C04-2114 2002 Microchip Technology Inc. B Units INCHES MIN NOM MAX p .026 BSC B .009 .011 .014 L .020 ...

Page 160

... A1 .015 E .595 .600 .625 E1 .530 .545 .560 D 2.045 2.058 2.065 L .120 .130 .135 c .008 .012 .015 B1 .030 .050 .070 B .014 .018 .022 eB .620 .650 .680 MILLIMETERS MIN NOM MAX 40 2.54 4.06 4.45 4.83 3.56 3.81 4.06 0.38 15.11 15.24 15.88 13.46 13.84 14.22 51.94 52.26 52.45 3.05 3.30 3.43 0.20 0.29 0.38 0.76 1.27 1.78 0.36 0.46 0.56 15.75 16.51 17. 2002 Microchip Technology Inc. ...

Page 161

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 2002 Microchip Technology Inc ...

Page 162

... E1 .650 .653 .656 D1 .650 .653 .656 E2 .590 .620 .630 D2 .590 .620 .630 c .008 .011 .013 B1 .026 .029 .032 B .013 .020 .021 MILLIMETERS MIN NOM MAX 44 1.27 11 4.19 4.39 4.57 3.68 3.87 4.06 0.51 0.71 0.89 0.61 0.74 0.86 1.02 1.14 1.27 0.00 0.13 0.25 17.40 17.53 17.65 17.40 17.53 17.65 16.51 16.59 16.66 16.51 16.59 16.66 14.99 15.75 16.00 14.99 15.75 16.00 0.20 0.27 0.33 0.66 0.74 0.81 0.33 0.51 0. 2002 Microchip Technology Inc. ...

Page 163

... FLASH Program Memory (14-bit words) Data Memory (bytes) I/O Ports A/D Parallel Slave Port Interrupt Sources Packages 2002 Microchip Technology Inc. APPENDIX B: The differences between the devices in this data sheet are listed in Table B-1. PIC16F73 PIC16F74 4K 4K 192 192 channels, 8 channels, 8 bits 8 bits ...

Page 164

... C Master/Slave) (SPI MHz 10-bit 2 4K, 8K FLASH 4K, 8K FLASH (1,000 E/W cycles) (100 E/W cycles typical) 192, 368 bytes 192, 368 bytes 128, 256 bytes In-Circuit Debugger, Low Voltage Programming 2002 Microchip Technology Inc. PIC16F7X 28/ Slave) 20 MHz 8-bit 2 None — ...

Page 165

... Analog Input Model .................................................... 86 Capture Mode Operation ........................................... 55 Compare .................................................................... 55 Crystal/Ceramic Resonator Operation (HS Osc Configuration) ........................... 91 External Clock Input Operation (HS Osc Configuration) ............................. 91 Interrupt Logic ............................................................ 99 PIC16F73 and PIC16F76 ............................................ 6 PIC16F74 and PIC16F77 ............................................ 7 PORTA RA3:RA0 and RA5 Port Pins ............................. 31 RA4/T0CKI Pin .................................................. 31 PORTB RB3:RB0 Port Pins ............................................ 33 RB7:RB4 Port Pins ............................................ 33 PORTC (Peripheral Output Override) ...

Page 166

... Interrupt-on-Change (RB7:RB4) Flag (RBIF bit) .................................... 21 RB0/INT Flag (INTF bit) ............................................ 21 TMR0 Overflow Flag (TMR0IF bit) .......................... 100 Evaluation and Programming Tools ................... 116 Load Conditions .............................................................. 125 Loading of PC .................................................................... Mode , 100 , 100 2002 Microchip Technology Inc. ...

Page 167

... Development Programmer ...................................... 115 , 10 PIE1 Register .................................................................... PIE2 Register .................................................................... Pinout Descriptions PIC16F73/PIC16F76 ...............................................8 PIC16F74/PIC16F77 ...........................................10 PIR1 Register .................................................................... 23 PIR2 Register .................................................................... 24 PMADR Register ............................................................... 29 PMADRH Register ............................................................ 29 POP ................................................................................... 26 POR. See Power-on Reset PORTA ..........................................................................8 Analog Port Pins ...................................................8 Associated Registers ................................................ 32 PORTA Register ....................................................... 31 RA4/T0CKI Pin ......................................................8 RA5/SS/AN4 Pin ...................................................8 TRISA Register ......................................................... 31 PORTA Register ...

Page 168

... RESET Conditions for All Registers .......................... RESET Conditions for PCON Register ..................... RESET Conditions for Program Counter ................... RESET Conditions for STATUS Register .................. RESET , 11 WDT Reset. See Watchdog Timer (WDT Revision History .............................................................. 161 , 11 – – 2002 Microchip Technology Inc. ...

Page 169

... Clock Source Select (T0CS bit) ................................. 20 External Clock ........................................................... 44 Interrupt ..................................................................... 43 Overflow Enable (TMR0IE bit) ................................... 21 Overflow Flag (TMR0IF bit) ..................................... 100 Overflow Interrupt .................................................... 100 Prescaler ................................................................... 45 RA4/T0CKI Pin, External Clock ............................ 8 T0CKI ........................................................................ 44 2002 Microchip Technology Inc. Timer1 ............................................................................... 47 Associated Registers ................................................ 50 Asynchronous Counter Mode .................................... 49 Capacitor Selection ................................................... 50 Counter Operation ..................................................... 48 Operation in Timer Mode .......................................... ...

Page 170

... Enable (WDTE Bit) .................................................. 101 Postscaler. See Postscaler, WDT Programming Considerations .................................. 101 RC Oscillator ........................................................... 101 Time-out Period ....................................................... 101 WDT Reset, Normal Operation .................... 93 WDT Reset, SLEEP ..................................... 93 WCOL bit ........................................................................... 61 Write Collision Detect bit (WCOL) ..................................... 61 WWW, On-Line Support ...................................................... 102 , 96 , 101 , , 2002 Microchip Technology Inc. ...

Page 171

... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2002 Microchip Technology Inc. PIC16F7X Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...

Page 172

... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30325B-page 170 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS30325B 2002 Microchip Technology Inc. ...

Page 173

... The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. XXX Examples: Pattern ...

Page 174

... Centro Direzionale Colleoni Palazzo Taurus Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/18/02 2002 Microchip Technology Inc. ...

Related keywords