PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 112/228:

AUSART SYNCHRONOUS MASTER RECEPTION

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PIC16F87/88
11.3.2
AUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled
by
setting
either
enable
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RB2/SDO/RX/DT pin on the falling
edge of the clock. If enable bit SREN is set, then only a
single word is received. If enable bit CREN is set, the
reception is continuous until CREN is cleared. If both
bits are set, CREN takes precedence.
After clocking the last bit, the received data in the
Receive Shift Register (RSR) is transferred to the
RCREG register (if it is empty). When the transfer is
complete, interrupt flag bit, RCIF (PIR1<5>), is set. The
actual interrupt can be enabled/disabled by setting/
clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read-only bit which is reset by the
hardware. In this case, it is reset when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It is
possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to begin
shifting into the RSR register. On the clocking of the last
bit of the third byte, if the RCREG register is still full, then
Overrun Error bit, OERR (RCSTA<1>), is set. The word
in the RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR has
to be cleared in software (by clearing bit CREN). If bit
OERR is set, transfers from the RSR to the RCREG are
inhibited, so it is essential to clear bit OERR if it is set.
The ninth receive bit is buffered the same way as the
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
0Bh, 8Bh,
INTCON
GIE
PEIE
10Bh,18Bh
(1)
0Ch
PIR1
ADIF
18h
RCSTA
SPEN
RX9
1Ah
RCREG
AUSART Receive Data Register
(1)
8Ch
PIE1
ADIE
98h
TXSTA
CSRC
TX9
99h
SPBRG
Baud Rate Generator Register
Legend:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
DS30487C-page 110
receive data. Reading the RCREG register will load bit
RX9D with a new value, therefore, it is essential for the
user to read the RCSTA register, before reading
RCREG, in order not to lose the old RX9D information.
bit
SREN
When setting up a synchronous master reception:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 11.1 “AUSART Baud Rate
Generator (BRG)”).
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3.
Ensure bits CREN and SREN are clear.
4.
If interrupts are desired, then set enable bit
RCIE.
5.
If 9-bit reception is desired, then set bit RX9.
6.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7.
Interrupt flag bit, RCIF, will be set when
reception is complete and an interrupt will be
generated if enable bit, RCIE, was set.
8.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF -000 0000
SREN
CREN
ADDEN
FERR
OERR
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE -000 0000
TXEN
SYNC
BRGH
TRMT
Value on
Value on:
Bit 0
all other
POR, BOR
Resets
RBIF
0000 000x
0000 000u
-000 0000
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
-000 0000
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
 2005 Microchip Technology Inc.