PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 113/228:

AUSART Synchronous Slave Mode

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FIGURE 11-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB2/SDO/RX/DT
bit 0
pin
RB5/SS/TX/CK
pin
Write to
bit SREN
SREN bit
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
11.4

AUSART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB5/SS/TX/CK pin (instead of being supplied inter-
nally in Master mode). This allows the device to trans-
fer or receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
11.4.1
AUSART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
The first word will immediately transfer to the
TSR register and transmit.
b)
The second word will remain in the TXREG register.
c)
Flag bit TXIF will not be set.
d)
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
Bit 6
0Bh, 8Bh,
INTCON
GIE
PEIE
10Bh,18Bh
(1)
0Ch
PIR1
ADIF
18h
RCSTA
SPEN
RX9
19h
TXREG
AUSART Transmit Data Register
(1)
8Ch
PIE1
ADIE
98h
TXSTA
CSRC
TX9
99h
SPBRG
Baud Rate Generator Register
Legend:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1:
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
 2005 Microchip Technology Inc.
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
bit 3
bit 4
bit 5
e)
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
When setting up a synchronous slave transmission,
follow these steps:
1.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2.
Clear bits CREN and SREN.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting enable bit
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the TXREG
register.
8.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
SREN
CREN ADDEN
FERR
OERR
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
TXEN
SYNC
BRGH
TRMT
PIC16F87/88
Q1 Q2 Q3 Q4
bit 6
bit 7
‘0’
Value on
Value on:
Bit 0
all other
POR, BOR
Resets
RBIF
0000 000x 0000 000u
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
DS30487C-page 111