PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 121/228:

Configuring Analog Port Pins

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12.4

Configuring Analog Port Pins

The ADCON1, ANSEL, TRISA and TRISB registers
control the operation of the A/D port pins. The port pins
that are desired as analog inputs must have their
corresponding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (V
will be converted.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the RA4:RA0 and
RB7:RB6 pins), may cause the input
buffer to consume current out of the
device specification.
FIGURE 12-3:
A/D CONVERSION T
T
to T
T
1
T
2
T
CY
AD
AD
AD
AD
b9
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
FIGURE 12-4:
A/D RESULT JUSTIFICATION
ADFM = 1
7
2 1 0 7
0000 00
ADRESH
ADRESL
10-bit Result
Right Justified
 2005 Microchip Technology Inc.
12.5
A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
or V
)
registers will continue to contain the value of the last
OH
OL
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 T
acquisition is started. After this 2 T
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 12-3, after the GO/DONE bit is set, the first
time segment has a minimum of T
T
.
AD
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
12.5.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 12-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
CYCLES
AD
3
T
4
T
5
T
6
T
7
T
8
AD
AD
AD
AD
AD
b8
b7
b6
b5
b4
b3
ADRES is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input
10-bit Result
0
7
ADRESH
10-bit Result
Left Justified
PIC16F87/88
wait is required before the next
AD
wait, acquisition
AD
and a maximum of
CY
10 T
11
T
9
T
AD
AD
AD
b2
b1
b0
ADFM = 0
0 7 6 5
0
0000 00
ADRESL
DS30487C-page 119