PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Page 141
142
Page 142
143
Page 143
144
Page 144
145
Page 145
146
Page 146
147
Page 147
148
Page 148
149
Page 149
150
Page 150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
Page 146/228:

FAIL-SAFE OPTION

Download datasheet (5Mb)Embed
PrevNext
PIC16F87/88
15.12.4

FAIL-SAFE OPTION

The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate even in the
event of an oscillator failure.
FIGURE 15-10:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
S
Q
Clock
INTRC
C
÷ 64
Q
Oscillator
31.25 kHz
488 Hz
(32 s)
(2.048 ms)
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word 2.
In the event of an oscillator failure, the FSCM will
generate an oscillator fail interrupt and will switch the
system clock over to the internal oscillator. The system
will continue to come from the internal oscillator until
the fail-safe condition is exited. The fail-safe condition
is exited with either a Reset, the execution of a SLEEP
instruction or a write to the OSCCON register.
The frequency of the internal oscillator will depend
upon the value contained in the IRCF bits. Another
clock source can be selected via the IRCF and the
SCS bits of the OSCCON register.
FIGURE 15-11:
FSCM TIMING DIAGRAM
Sample Clock
(488 Hz)
System
Clock
Output
CM Output
(Q)
OSFIF
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS30487C-page 144
The FSCM sample clock is generated by dividing the
INTRC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur.
On the rising edge of the postscaled clock, the
monitoring latch (CM = 0) will be cleared. On a falling
edge of the primary or secondary system clock, the
monitoring latch will be set (CM = 1). In the event that
a falling edge of the postscaled clock occurs and the
monitoring latch is not set, a clock failure has been
detected.
While in Fail-Safe mode, a Reset will exit the fail-safe
condition. If the primary clock source is configured for
a crystal, the OST timer will wait for the 1024 clock
cycles for the OST time-out and the device will
continue running from the internal oscillator until the
OST is complete. A SLEEP instruction, or a write to the
SCS bits (where SCS bits do not = 00), can be
Clock
performed to put the device into a low-power mode.
Failure
Note:
Two-Speed Start-up mode is automatically
Detected
enabled when the fail-safe option is
enabled.
If Reset occurs while in Fail-Safe mode and the pri-
mary clock source is EC or RC, then the device will
immediately switch back to EC or RC mode.
15.12.4.1
Fail-Safe in Low-Power Mode
A write to the OSCCON register, or SLEEP instruction,
will end the fail-safe condition. The system clock will
default to the source selected by the SCS bits, which
is either T1OSC, INTRC or none (Sleep mode). How-
ever, the FSCM will continue to monitor the system
clock. If the secondary clock fails, the device will
immediately switch to the internal oscillator clock. If
OSFIE is set, an interrupt will be generated.
Oscillator
Failure
CM Test
Failure
Detected
CM Test
 2005 Microchip Technology Inc.