PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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PIC16F87/88
15.13.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin.
2.
Watchdog Timer wake-up (if WDT was enabled).
3.
Interrupt from INT pin, RB port change or a
peripheral interrupt.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred and caused
wake-up.
The following peripheral interrupts can wake the device
from Sleep:
1.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2.
CCP Capture mode interrupt.
3.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
4.
SSP (Start/Stop) bit detect interrupt.
5.
SSP transmit or receive in Slave mode (SPI/I
6.
A/D conversion (when A/D clock source is RC).
7.
EEPROM write operation completion.
8.
Comparator output changes state.
9.
AUSART RX or TX (Synchronous Slave mode).
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
FIGURE 15-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
(4)
CLKO
INT pin
INT0IF Flag
(INTCON<1>)
(3)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC + 1
Instruction
Inst(PC + 1)
Inst(PC) = Sleep
Fetched
Instruction
Sleep
Inst(PC – 1)
Executed
Note
1:
XT, HS or LP Oscillator mode assumed.
2:
T
= 1024 T
(drawing not to scale). This delay will not be there for RC Oscillator mode.
OST
OSC
3:
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine.
If GIE = 0, execution will continue in-line.
4:
CLKO is not available in these oscillator modes, but shown here for timing reference.
DS30487C-page 146
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the execu-
tion of the instruction following SLEEP is not desirable,
the user should have a NOP after the SLEEP instruction.
15.13.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
2
and postscaler (if enabled) will be cleared, the TO
C).
bit will be set and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(2)
T
OST
Interrupt Latency
(Note 2)
Processor in
Sleep
PC + 2
PC + 2
PC + 2
Inst(PC + 2)
Dummy Cycle
Inst(PC + 1)
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
 2005 Microchip Technology Inc.