PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Page 151
152
Page 152
153
Page 153
154
Page 154
155
Page 155
156
Page 156
157
Page 157
158
Page 158
159
Page 159
160
Page 160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
Page 152/228

Download datasheet (5Mb)Embed
PrevNext
PIC16F87/88
TABLE 16-2:
PIC16F87/88 INSTRUCTION SET
Mnemonic,
Description
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f, d
Add W and f
ANDWF
f, d
AND W with f
CLRF
f
Clear f
CLRW
-
Clear W
COMF
f, d
Complement f
DECF
f, d
Decrement f
DECFSZ
f, d
Decrement f, Skip if 0
INCF
f, d
Increment f
INCFSZ
f, d
Increment f, Skip if 0
IORWF
f, d
Inclusive OR W with f
MOVF
f, d
Move f
MOVWF
f
Move W to f
NOP
-
No Operation
RLF
f, d
Rotate Left f through Carry
RRF
f, d
Rotate Right f through Carry
SUBWF
f, d
Subtract W from f
SWAPF
f, d
Swap nibbles in f
XORWF
f, d
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b
Bit Clear f
BSF
f, b
Bit Set f
BTFSC
f, b
Bit Test f, Skip if Clear
BTFSS
f, b
Bit Test f, Skip if Set
ADDLW
k
Add literal and W
ANDLW
k
AND literal with W
CALL
k
Call subroutine
CLRWDT
-
Clear Watchdog Timer
GOTO
k
Go to address
IORLW
k
Inclusive OR literal with W
MOVLW
k
Move literal to W
RETFIE
-
Return from interrupt
RETLW
k
Return with literal in W
RETURN
-
Return from Subroutine
SLEEP
-
Go into Standby mode
SUBLW
k
Subtract W from literal
XORLW
k
Exclusive OR literal with W
Note 1:
When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2:
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3:
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the “PICmicro
Family Reference Manual” (DS33023).
DS30487C-page 150
Cycles
MSb
1
00
1
00
1
00
1
00
1
00
1
00
1(2)
00
1
00
1(2)
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
01
1
01
1 (2)
01
1 (2)
01
LITERAL AND CONTROL OPERATIONS
1
11
1
11
2
10
1
00
2
10
1
11
1
11
2
00
2
11
2
00
1
00
1
11
1
11
14-Bit Opcode
Status
Notes
Affected
LSb
C,DC,Z
1,2
0111
dfff
ffff
Z
1,2
0101
dfff
ffff
Z
2
0001
lfff
ffff
Z
0001
0xxx
xxxx
Z
1,2
1001
dfff
ffff
Z
1,2
0011
dfff
ffff
1,2,3
1011
dfff
ffff
Z
1,2
1010
dfff
ffff
1,2,3
1111
dfff
ffff
Z
1,2
0100
dfff
ffff
Z
1,2
1000
dfff
ffff
0000
lfff
ffff
0000
0xx0
0000
C
1,2
1101
dfff
ffff
C
1,2
1100
dfff
ffff
C,DC,Z
1,2
0010
dfff
ffff
1,2
1110
dfff
ffff
Z
1,2
0110
dfff
ffff
1,2
00bb
bfff
ffff
1,2
01bb
bfff
ffff
3
10bb
bfff
ffff
3
11bb
bfff
ffff
C,DC,Z
111x
kkkk
kkkk
Z
1001
kkkk
kkkk
0kkk
kkkk
kkkk
PD
TO
0000
0110
0100
,
1kkk
kkkk
kkkk
Z
1000
kkkk
kkkk
00xx
kkkk
kkkk
0000
0000
1001
01xx
kkkk
kkkk
0000
0000
1000
TO
PD
0000
0110
0011
,
C,DC,Z
110x
kkkk
kkkk
Z
1010
kkkk
kkkk
®
Mid-Range MCU
 2005 Microchip Technology Inc.