PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 16/228:

SPECIAL FUNCTION REGISTERS

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PIC16F87/88
2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bank 0
(2)
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
01h
TMR0
Timer0 Module Register
(2)
02h
PCL
Program Counter (PC) Least Significant Byte
(2)
03h
STATUS
IRP
RP1
(2)
04h
FSR
Indirect Data Memory Address Pointer
05h
PORTA
PORTA Data Latch when written; PORTA pins when read (PIC16F87)
PORTA Data Latch when written; PORTA pins when read (PIC16F88)
06h
PORTB
PORTB Data Latch when written; PORTB pins when read (PIC16F87)
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
(1,2)
0Ah
PCLATH
(2)
0Bh
INTCON
GIE
PEIE
(4)
0Ch
PIR1
ADIF
0Dh
PIR2
OSFIF
CMIF
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
T1RUN
11h
TMR2
Timer2 Module Register
12h
T2CON
TOUTPS3 TOUTPS2
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
WCOL
SSPOV
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
17h
CCP1CON
18h
RCSTA
SPEN
RX9
19h
TXREG
AUSART Transmit Data Register
1Ah
RCREG
AUSART Receive Data Register
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
(4)
1Eh
ADRESH
A/D Result Register High Byte
(4)
1Fh
ADCON0
ADCS1
ADCS0
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
4:
PIC16F88 device only.
DS30487C-page 14
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
Bit 5
Bit 4
Bit 3
Bit 2
RP0
TO
PD
Z
Write Buffer for the Upper 5 bits of the Program Counter
TMR0IE
INT0IE
RBIE
TMR0IF
RCIF
TXIF
SSPIF
CCP1IF
EEIF
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TOUTPS1
TOUTPS0
TMR2ON
SSPEN
CKP
SSPM3
SSPM2
CCP1X
CCP1Y
CCP1M3
CCP1M2
SREN
CREN
ADDEN
FERR
CHS2
CHS1
CHS0
GO/DONE
Details
Value on:
Bit 1
Bit 0
on
POR, BOR
page
26, 135
0000 0000
69
xxxx xxxx
0000 0000
DC
C
17
0001 1xxx
135
xxxx xxxx
52
xxxx 0000
xxx0 0000
58
xxxx xxxx
00xx xxxx
135
---0 0000
INT0IF
RBIF
19, 69,
0000 000x
77
TMR2IF
TMR1IF
21, 77
-000 0000
23, 34
00-0 ----
77, 83
xxxx xxxx
77, 83
xxxx xxxx
TMR1CS
TMR1ON
72, 83
-000 0000
80, 85
0000 0000
T2CKPS1
T2CKPS0
80, 85
-000 0000
90, 95
xxxx xxxx
SSPM1
SSPM0
89, 95
0000 0000
83, 85
xxxx xxxx
83, 85
xxxx xxxx
CCP1M1
CCP1M0
81, 83
--00 0000
OERR
RX9D
98, 99
0000 000x
103
0000 0000
105
0000 0000
120
xxxx xxxx
ADON
0000 00-0 114, 120
 2005 Microchip Technology Inc.