PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
Page 181
182
Page 182
183
Page 183
184
Page 184
185
Page 185
186
Page 186
187
Page 187
188
Page 188
189
Page 189
190
Page 190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
Page 190/228:

I C BUS DATA REQUIREMENTS

Download datasheet (5Mb)Embed
PrevNext
PIC16F87/88
2
TABLE 18-10: I
C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
No.
100*
T
Clock High Time
HIGH
101*
T
Clock Low Time
LOW
102*
T
SDA and SCL Rise
R
Time
103*
T
SDA and SCL Fall
F
Time
90*
T
:
Start Condition
SU
STA
Setup Time
91*
T
:
Start Condition Hold
HD
STA
Time
106*
T
:
Data Input Hold
HD
DAT
Time
107*
T
:
Data Input Setup
SU
DAT
Time
92*
T
:
Stop Condition
SU
STO
Setup Time
109*
T
Output Valid from
AA
Clock
110*
T
Bus Free Time
BUF
C
Bus Capacitive Loading
B
*
These parameters are characterized but not tested.
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2:
A Fast mode (400 kHz) I
C™ bus device can be used in a Standard mode (100 kHz) I
the requirement, T
:
SU
DAT
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line, T
2
Standard mode I
C bus specification), before the SCL line is released.
DS30487C-page 188
Min
Max
100 kHz mode
4.0
400 kHz mode
0.6
SSP Module
1.5 T
CY
100 kHz mode
4.7
400 kHz mode
1.3
SSP Module
1.5 T
CY
100 kHz mode
1000
400 kHz mode
20 + 0.1 C
300
B
100 kHz mode
300
400 kHz mode
20 + 0.1 C
300
B
100 kHz mode
4.7
400 kHz mode
0.6
100 kHz mode
4.0
400 kHz mode
0.6
100 kHz mode
0
400 kHz mode
0
100 kHz mode
250
400 kHz mode
100
100 kHz mode
4.7
400 kHz mode
0.6
100 kHz mode
3500
400 kHz mode
100 kHz mode
4.7
400 kHz mode
1.3
250 ns, must then be met. This will automatically be the case if the device does
max. + T
:
R
SU
DAT
Units
Conditions
s
s
s
s
ns
ns
C
is specified to be from
B
10-400 pF
ns
ns
C
is specified to be from
B
10-400 pF
s
Only relevant for
Repeated Start
s
condition
s
After this period, the first
clock pulse is generated
s
ns
0.9
s
ns
(Note 2)
ns
s
s
ns
(Note 1)
ns
s
Time the bus must be free
before a new transmission
s
can start
400
pF
2
C bus system, but
= 1000 + 250 = 1250 ns (according to the
 2005 Microchip Technology Inc.