PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 191/228:

AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

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FIGURE 18-16:
AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RB5/SS/TX/CK
121
pin
RB2/SDO/RX/DT
pin
120
Note: Refer to Figure 18-3 for load conditions.
TABLE 18-11: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Sym
No.
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
Clock High to Data Out Valid
121
Tckrf
Clock Out Rise Time and Fall
Time (Master mode)
122
Tdtrf
Data Out Rise Time and Fall
Time
Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 18-17:
AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RB5/SS/TX/CK
pin
RB2/SDO/RX/DT
pin
Note: Refer to Figure 18-3 for load conditions.
TABLE 18-12: AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Sym
Characteristic
No.
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data Setup before CK
126
TckL2dtl
Data Hold after CK
† Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2005 Microchip Technology Inc.
121
Characteristic
Min
PIC16F87/88
PIC16LF87/88
PIC16F87/88
PIC16LF87/88
PIC16F87/88
PIC16LF87/88
125
126
Min
Typ†
(DT setup time)
15
(DT hold time)
15
PIC16F87/88
122
Typ†
Max
Units Conditions
80
ns
100
ns
45
ns
50
ns
45
ns
50
ns
Max
Units
Conditions
ns
ns
DS30487C-page 189