PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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PIC16F87/88
S
SCI. See AUSART.
SCL .................................................................................... 93
Serial Communication Interface. See AUSART.
Slave Mode
SCL ............................................................................ 93
SDA ............................................................................ 93
Sleep ................................................................ 129, 132, 145
Software Simulator (MPLAB SIM) .................................... 158
Software Simulator (MPLAB SIM30) ................................ 158
SPBRG Register ................................................................ 15
Special Event Trigger ....................................................... 120
Special Features of the CPU ............................................ 129
Special Function Registers ................................................ 14
Special Function Registers (SFRs) .................................... 14
SPI
Associated Registers ................................................. 90
Serial Clock ................................................................ 87
Serial Data In ............................................................. 87
Serial Data Out .......................................................... 87
Slave Select ............................................................... 87
SSP
ACK ............................................................................ 93
2
I
C
2
I
C Operation ..................................................... 92
SSPADD Register .............................................................. 15
SSPBUF Register .............................................................. 14
SSPCON Register .............................................................. 14
SSPOV ............................................................................... 89
SSPOV Bit .......................................................................... 93
SSPSTAT Register ............................................................ 15
Stack .................................................................................. 25
Overflows ................................................................... 25
Underflow ................................................................... 25
STATUS Register
C Bit ........................................................................... 17
DC Bit ......................................................................... 17
IRP Bit ........................................................................ 17
PD Bit ................................................................. 17, 132
RP Bits ....................................................................... 17
TO Bit ................................................................. 17, 132
Z Bit ............................................................................ 17
Synchronous Master Reception
Associated Registers ............................................... 110
Synchronous Master Transmission
Associated Registers ............................................... 109
Synchronous Serial Port (SSP) .......................................... 87
Overview .................................................................... 87
SPI Mode ................................................................... 87
Synchronous Slave Reception
Associated Registers ............................................... 112
Synchronous Slave Transmission
Associated Registers ............................................... 111
T
T1CKPS0 Bit ...................................................................... 72
T1CKPS1 Bit ...................................................................... 72
T1CON Register ................................................................. 14
T1OSCEN Bit ..................................................................... 72
T1SYNC Bit ........................................................................ 72
T2CKPS0 Bit ...................................................................... 80
T2CKPS1 Bit ...................................................................... 80
T2CON Register ................................................................. 14
T
................................................................................... 118
AD
Time-out Sequence .......................................................... 134
DS30487C-page 220
Timer0 ................................................................................ 67
Associated Registers ................................................. 69
Clock Source Edge Select (T0SE Bit) ....................... 18
Clock Source Select (T0CS Bit) ................................. 18
External Clock ............................................................ 68
Interrupt ..................................................................... 67
Operation ................................................................... 67
Overflow Enable (TMR0IE Bit) ................................... 19
Overflow Flag (TMR0IF Bit) ..................................... 140
Overflow Interrupt .................................................... 140
Prescaler ................................................................... 68
T0CKI ........................................................................ 68
Timer1 ................................................................................ 71
Associated Registers ................................................. 77
Capacitor Selection .................................................... 75
Counter Operation ..................................................... 73
Operation ................................................................... 71
Operation in Asynchronous Counter Mode ................ 74
Reading and Writing .......................................... 74
Operation in Synchronized Counter Mode ................. 73
Operation in Timer Mode ........................................... 73
Oscillator .................................................................... 75
Oscillator Layout Considerations ............................... 75
Prescaler ................................................................... 76
Resetting Timer1 Register Pair .................................. 76
Resetting Timer1 Using a CCP Trigger Output ......... 76
Use as a Real-Time Clock ......................................... 76
Timer2 ................................................................................ 79
Associated Registers ................................................. 80
Output ........................................................................ 79
Postscaler .................................................................. 79
Prescaler ................................................................... 79
Prescaler and Postscaler ........................................... 79
Timing Diagrams
A/D Conversion ........................................................ 191
Asynchronous Master Transmission ........................ 103
Asynchronous Master Transmission
(Back to Back) ................................................. 103
Asynchronous Reception ......................................... 104
Asynchronous Reception with
Address Byte First ........................................... 107
Asynchronous Reception with
Address Detect ................................................ 107
AUSART Synchronous Receive
(Master/Slave) ................................................. 189
AUSART Synchronous Transmission
(Master/Slave) ................................................. 189
Brown-out Reset ...................................................... 181
Capture/Compare/PWM (CCP1) ............................. 183
CLKO and I/O .......................................................... 180
External Clock .......................................................... 179
Fail-Safe Clock Monitor ........................................... 144
2
I
C Bus Data ............................................................ 187
2
I
C Bus Start/Stop Bits ............................................ 186
2
I
C Reception (7-Bit Address) ................................... 94
2
I
C Transmission (7-Bit Address) .............................. 94
Primary System Clock After Reset
(EC, RC, INTRC) ............................................... 48
Primary System Clock After Reset
(HS, XT, LP) ...................................................... 47
PWM Output .............................................................. 84
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer .............................. 181
Slow Rise Time (MCLR Tied to V
DD
Through RC Network) ...................................... 138
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