PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 34/228:

Writing to Flash Program Memory

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PIC16F87/88
3.7

Writing to Flash Program Memory

Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT1:WRT0 of
the device Configuration Word (Register 15-1). Flash
program memory must be written in four-word blocks.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where EEADR<1:0> = 00. At the same time,
all block writes to program memory are done as write-
only operations. The program memory must first be
erased. The write operation is edge-aligned and cannot
occur across boundaries.
To write to the program memory, the data must first be
loaded into the buffer registers. There are four 14-bit
buffer registers and they are addressed by the low
2 bits of EEADR.
The following sequence of events illustrate how to
perform a write to program memory:
• Set the EEPGD and WREN bits in the EECON1
register
• Clear the FREE bit in EECON1
• Write address to EEADRH:EEADR
• Write data to EEDATH:EEDATA
• Write 55 to EECON2
• Write AA to EECON2
• Set WR bit in EECON1
FIGURE 3-1:
BLOCK WRITES TO FLASH PROGRAM MEMORY
7
First word of block
to be written
14
EEADR<1:0>
EEADR<1:0>
=
= 01
00
Buffer Register
DS30487C-page 32
The user must follow the same specific sequence to
initiate the write for each word in the program block
by writing each program word in sequence (00, 01,
10, 11).
There are 4 buffer register words and all four locations
MUST be written to with correct data.
After the “BSF EECON1,
EEADR
xxxxxx11, then a short write will occur.
This short write only transfers the data to the buffer
register. The WR bit will be cleared in hardware after
1 cycle.
After the “BSF EECON1,
EEADR = xxxxxx11, then a long write will occur. This
will
simultaneously
EEDATH:EEDATA to the buffer registers and begin the
write of all four words. The processor will execute the
next instruction and then ignore the subsequent
instruction. The user should place NOP instructions into
the second words. The processor will then halt internal
operations for typically 2 msec in which the write takes
place. This is not Sleep mode, as the clocks and
peripherals will continue to run. After the write cycle,
the processor will resume operation with the 3rd
instruction after the EECON1 write instruction.
After each long write, the 4 buffer registers will be reset
to 3FFF.
5
0 7
EEDATH
EEDATA
6
8
14
14
EEADR<1:0>
= 10
Buffer Register
Buffer Register
Program Memory
WR” instruction, if
WR” instruction, if
transfer
the
data
from
0
All buffers are
transferred
to Flash
automatically
after this word
is written
14
EEADR<1:0>
= 11
Buffer Register
 2005 Microchip Technology Inc.