PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 42/228:

CLOCK TRANSITION AND WDT

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PIC16F87/88
4.6.3

CLOCK TRANSITION AND WDT

When clock switching is performed, the Watchdog
Timer is disabled because the Watchdog ripple counter
is used as the Oscillator Start-up Timer.
Note:
The OST is only used when switching to
XT, HS and LP Oscillator modes.
REGISTER 4-2:
OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
U-0
R/W-0
IRCF2
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF<2:0>: Internal RC Oscillator Frequency Select bits
000 = 31.25 kHz
001 = 125 kHz
010 = 250 kHz
011 = 500 kHz
100 = 1 MHz
101 = 2 MHz
110 = 4 MHz
111 = 8 MHz
bit 3
OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the primary system clock
0 = Device is running from T1OSC or INTRC as a secondary system clock
Note 1: Bit resets to ‘0’ with Two-Speed Start-up mode and LP, XT or HS selected as the
oscillator mode.
bit 2
IOFS: INTOSC Frequency Stable bit
1 = Frequency is stable
0 = Frequency is not stable
bit 1-0
SCS<1:0>: Oscillator Mode Select bits
00 = Oscillator mode defined by FOSC<2:0>
01 = T1OSC is used for system clock
10 = Internal RC is used for system clock
11 = Reserved
Legend:
R = Readable bit
-n = Value at POR
DS30487C-page 40
Once the clock transition is complete (i.e., new oscilla-
tor selection switch has occurred), the Watchdog
counter is re-enabled with the counter reset. This
allows the user to synchronize the Watchdog Timer to
the start of execution at the new clock frequency.
R/W-0
R/W-0
R-0
R/W-0
(1)
IRCF1
IRCF0
OSTS
IOFS
(1)
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
 2005 Microchip Technology Inc.
R/W-0
R/W-0
SCS1
SCS0
bit 0
x = Bit is unknown