PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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FIGURE 4-6:
PIC16F87/88 CLOCK DIAGRAM
Primary Oscillator
OSC2
Sleep
OSC1
Secondary Oscillator
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
Internal
Oscillator
Block
31.25 kHz
Source
31.25 kHz
(INTRC)
4.6.4
MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. If the INTRC
(31.25 kHz, IRCF<2:0> = 000) is running and the IRCF
bits are modified to any other value than ‘000’, a 4 ms
(approx.) clock switch delay is turned on. Code execu-
tion continues at a higher than expected frequency
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. This bit can be moni-
tored to ensure that the frequency is stable before using
the system clock in time critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF<2:0>
000), there is no need for a
4 ms (approx.) clock switch delay. The new INTOSC
frequency will be stable immediately after the eight fall-
ing edges. The IOFS bit will remain set after clock
switching occurs.
Note:
Caution must be taken when modifying the
IRCF bits using BCF or BSF instructions. It
is possible to modify the IRCF bits to a
frequency that may be out of the V
ification range; for example, V
and IRCF = 111 (8 MHz).
 2005 Microchip Technology Inc.
LP, XT, HS, RC, EC
To Timer1
OSCCON<6:4>
8 MHz
111
4 MHz
110
2 MHz
101
1 MHz
100
500 kHz
8 MHz
011
(INTOSC)
250 kHz
010
125 kHz
001
31.25 kHz
000
4.6.5
CLOCK TRANSITION SEQUENCE
Following are three different sequences for switching
the internal RC oscillator frequency.
• Clock before switch: 31.25 kHz (IRCF<2:0> = 000)
1.
IRCF bits are modified to an INTOSC/INTOSC
postscaler frequency.
2.
The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3.
The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4.
The IOFS bit is clear to indicate that the clock is
unstable and a 4 ms (approx.) delay is started.
Time dependent code should wait for IOFS to
become set.
5.
Switchover is complete.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0>
1.
IRCF
bits
(IRCF<2:0> = 000).
2.
The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3.
The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
spec-
DD
4.
Oscillator switchover is complete.
= 2.0V
DD
PIC16F87/88
Configuration Word 1 (FOSC2:FOSC0)
SCS<1:0> (T1OSC)
Peripherals
T1OSC
Internal Oscillator
CPU
WDT, FSCM
000)
are
modified
to
INTRC
DS30487C-page 41

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