PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 45/228:

Power-Managed Modes

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4.7

Power-Managed Modes

4.7.1
RC_RUN MODE
When SCS bits are configured to run from the INTRC,
a clock transition is generated if the system clock is
not already using the INTRC. The event will clear the
OSTS bit, switch the system clock from the primary
system clock (if SCS<1:0> = 00) determined by the
value contained in the configuration bits, or from the
T1OSC (if SCS<1:0> = 01) to the INTRC clock option
and shut down the primary system clock to conserve
power. Clock switching will not occur if the primary
system clock is already configured as INTRC.
FIGURE 4-7:
TIMING DIAGRAM FOR XT, HS, LP, EC AND EXTRC TO RC_RUN MODE
Q1
Q2
Q3
Q4
Q1
(1)
T
INP
INTOSC
OSC1
OSC (2)
T
System
Clock
(4)
T
DLY
SCS<1:0>
Program
PC
Counter
Note 1:
T
= 32 s typical.
INP
2:
T
= 50 ns minimum.
OSC
3:
T
= 8 T
.
SCS
INP
4:
T
= 1 T
.
DLY
INP
 2005 Microchip Technology Inc.
PIC16F87/88
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after 4 ms (approx.).
After a clock switch has been executed, the OSTS bit
is cleared, indicating a low-power mode and the
device does not run from the primary system clock.
The internal Q clocks are held in the Q1 state until
eight falling edge clocks are counted on the INTRC
oscillator.
After
the
transpired, the clock input to the Q clocks is released
and operation resumes (see Figure 4-7).
Q2
Q3
Q4
Q1
SCS (3)
T
PC + 1
eight
clock
periods
have
Q1
Q2
Q1
Q3
Q4
PC + 2
PC + 3
DS30487C-page 43