PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
Page 52/228:

EXITING SLEEP WITH AN INTERRUPT

Download datasheet (5Mb)Embed
PrevNext
PIC16F87/88
4.7.4
EXITING SLEEP WITH AN
INTERRUPT
Any interrupt, such as WDT or INT0, will cause the part
to leave the Sleep mode.
The SCS bits are unaffected by a SLEEP command and
are the same before and after entering and leaving
Sleep. The clock source used after an exit from Sleep
is determined by the SCS bits.
4.7.4.1
Sequence of Events
If SCS<1:0> = 00:
1.
The device is held in Sleep until the CPU start-up
time-out is complete.
2.
If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST will
be active waiting for 1024 clocks of the primary
system clock. While waiting for the OST, the
device will be held in Sleep unless Two-Speed
Start-up is enabled. The OST and CPU start-up
timers run in parallel. Refer to Section 15.12.3
“Two-Speed Clock Start-up Mode” for details
on Two-Speed Start-up.
3.
After both the CPU start-up and OST timers
have timed out, the device will exit Sleep and
begin instruction execution with the primary
clock defined by the FOSC bits.
DS30487C-page 50
If SCS<1:0> = 01 or 10:
1.
The device is held in Sleep until the CPU start-up
time-out is complete.
2.
After the CPU start-up timer has timed out, the
device will exit Sleep and begin instruction
execution with the selected oscillator mode.
Note:
If a user changes SCS<1:0> just before
entering Sleep mode, the system clock
used when exiting Sleep mode could be
different than the system clock used when
entering Sleep mode.
As an example, if SCS<1:0> = 01 and
T1OSC is the system clock and the
following instructions are executed:
BCF
OSCCON, SCS0
SLEEP
then a clock change event is executed. If
the primary oscillator is XT, LP or HS, the
core will continue to run off T1OSC and
execute the SLEEP command.
When Sleep is exited, the part will resume
operation with the primary oscillator after
the OST has expired.
 2005 Microchip Technology Inc.