PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 70/228:

Using Timer0 with an External Clock

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PIC16F87/88
6.3
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 T
a small RC delay of 20 ns) and low for at least 2 T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.4
Prescaler
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that the prescaler cannot be
used by the Watchdog Timer and vice versa. This
prescaler is not readable or writable (see Figure 6-1).
REGISTER 6-1:
OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
bit 7
bit 7
RBPU: PORTB Pull-up Enable bit
bit 6
INTEDG: Interrupt Edge Select bit
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
1 : 2
000
1 : 4
001
1 : 8
010
1 : 16
011
1 : 32
100
1 : 64
101
1 : 128
110
1 : 256
111
Legend:
R = Readable bit
-n = Value at POR
Note:
To avoid an unintended device Reset, the instruction sequence shown in the
”PICmicro
executed when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.
DS30487C-page 68
Note:
Although the prescaler can be assigned to
either the WDT or Timer0, but not both, a
new divide counter is implemented in the
WDT circuit to give multiple WDT time-out
selections. This allows TMR0 and WDT to
each have their own scaler. Refer to
Section 15.12 “Watchdog Timer (WDT)”
for further details.
(and
OSC
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
OSC
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Note:
Writing to TMR0, when the prescaler is
assigned
prescaler count but will not change the
prescaler assignment.
R/W-1
R/W-1
R/W-1
R/W-1
INTEDG
T0CS
T0SE
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
®
Mid-Range MCU Family Reference Manual” (DS33023) must be
to
Timer0,
will
clear
the
R/W-1
R/W-1
R/W-1
PSA
PS2
PS1
PS0
bit 0
x = Bit is unknown
 2005 Microchip Technology Inc.