PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 91/228:

SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER

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REGISTER 10-2:
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
WCOL
SSPOV
bit 7
bit 7
WCOL: Write Collision Detect bit
1 = An attempt to write the SSPBUF register failed because the SSP module is busy
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master
mode, the overflow bit is not set since each new reception (and transmission) is initiated
by writing to the SSPBUF register.
0 = No overflow
2
In I
C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is
a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I
C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note 1: In both modes, when enabled, these pins must be properly configured as input or
output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Transmit happens on falling edge, receive on rising edge. Idle state for clock is a high level.
0 = Transmit happens on rising edge, receive on falling edge. Idle state for clock is a low level.
2
In I
C Slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = OSC/4
0001 = SPI Master mode, clock = OSC/16
0010 = SPI Master mode, clock = OSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
2
0110 = I
C Slave mode, 7-bit address
2
0111 = I
C Slave mode, 10-bit address
2
1011 = I
C Firmware Controlled Master mode (Slave Idle)
2
1110 = I
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
2
1111 = I
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1000, 1001, 1010, 1100, 1101 = Reserved
Legend:
R = Readable bit
-n = Value at POR
 2005 Microchip Technology Inc.
R/W-0
R/W-0
R/W-0
(1)
SSPEN
CKP
SSPM3
(1)
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
PIC16F87/88
R/W-0
R/W-0
R/W-0
SSPM2
SSPM1
SSPM0
bit 0
x = Bit is unknown
DS30487C-page 89