PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 94/228:

C Mode Operation

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PIC16F87/88
2
10.3
SSP I

C Mode Operation

2
The SSP module in I
C mode fully implements all slave
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP
module
implements
the
standard
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RB4/
SCK/SCL pin, which is the clock (SCL) and the RB1/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISB<4,1> bits.
EXAMPLE 10-1:
MOVF
TRISC, W
; Example for an 18-pin part such as the PIC16F818/819
IORLW
0x18
; Ensures <4:3> bits are ‘11’
ANDLW
B’11111001’
; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF
TRISC
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON<5>).
FIGURE 10-5:
SSP BLOCK DIAGRAM
2
(I
C™ MODE)
Read
Write
RB4/SCK/
SSPBUF Reg
SCL
Shift
Clock
SSPSR Reg
RB1/
MSb
LSb
SDI/
SDA
Match Detect
SSPADD Reg
Start and
Stop Bit Detect
The SSP module has five registers for I
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer register (SSPBUF)
• SSP Shift register (SSPSR) – Not directly
accessible
• SSP Address register (SSPADD)
DS30487C-page 92
To ensure proper communication of the I
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
2
I
C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>)
of the port containing the I
are changed in software during I
using a Read-Modify-Write instruction (BSF, BCF), then
mode
2
the I
C mode may stop functioning properly and I
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I
using the instruction BSF or BCF during I
tion. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
• I
C Slave mode (7-bit address)
2
• I
C Slave mode (10-bit address)
2
Internal
• I
C Slave mode (7-bit address) with Start and
Data Bus
Stop bit interrupts enabled to support Firmware
Controlled Master mode
2
• I
C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Controlled Master mode
2
• I
C Firmware Controlled Master mode operation
with Start and Stop bit interrupts enabled; slave is
Idle
Selection of any I
forces the SCL and SDA pins to be open-drain, pro-
Addr Match
vided these pins are programmed to inputs by setting
the appropriate TRISB bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
Set, Reset
S, P Bits
Additional information on SSP I
(SSPSTAT Reg)
found in the “PICmicro
Reference Manual” (DS33023).
2
C operation:
2
C Slave mode,
2
C pins (PORTx [SDA, SCL])
2
C communication
2
C
2
C pins)
2
C communica-
2
C opera-
2
C modes to be selected:
2
C mode, with the SSPEN bit set,
2
C module.
2
C operation may be
®
Mid-Range MCU Family
 2005 Microchip Technology Inc.