PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 96/228:

I C WAVEFORMS FOR RECEPTION

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PIC16F87/88
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF, must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit, SSPIF, is set on the falling edge of
the ninth clock pulse.
As a slave transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
TABLE 10-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR
BF
SSPOV
Yes
0
0
No
1
0
No
1
1
No
0
1
Note 1:
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
2
FIGURE 10-6:
I
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
R/W = 0
A7 A6 A5 A4 A3 A2 A1
SDA
3
6
7
1
2
4
5
8
SCL
S
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
2
FIGURE 10-7:
I
C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
SDA
A7
A6
A5
A4
A3
SCL
1
2
3
4
5
S
Data is
sampled
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
DS30487C-page 94
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is reset (resets
SSPSTAT register) and the slave device then monitors
for another occurrence of the Start bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register which also loads the SSPSR
register. Then, pin RB4/SCK/SCL should be enabled
by setting bit CKP.
SSPBUF
Generate ACK Pulse
Yes
No
No
No
Receiving Data
ACK
ACK
D7
D6
D5
D4
D3
D2
D1
D0
D7
3
7
9
1
2
4
5
6
8
9
1
Cleared in software
SSPBUF register is read
Bit SSPOV is set because the SSPBUF register is still full
R/W = 1
A2
A1
ACK
D7
D6
6
7
8
9
1
2
SCL held low
while CPU
responds to SSPIF
Cleared in software
SSPBUF is written in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
Set SSPIF Bit
(SSP Interrupt Occurs if Enabled)
Yes
Yes
Yes
Yes
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
9
2
3
5
6
7
8
4
P
Bus master
terminates
transfer
ACK is not sent
Transmitting Data
ACK
D5
D4
D3
D2
D1
D0
3
4
5
6
7
8
9
P
From SSP Interrupt
Service Routine
 2005 Microchip Technology Inc.