PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 97/228:

MASTER MODE OPERATION

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10.3.2

MASTER MODE OPERATION

Master mode operation is supported in firmware using
interrupt generation on the detection of the Start and
Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset, or when the SSP module is dis-
abled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I
may be taken when the P bit is set, or the bus is Idle
and both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low, irre-
spective of the value(s) in PORTB<4,1>. So, when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
2
SDA pins for proper operation of the I
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode Idle (SSPM3:SSPM0 = 1011), or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Master mode operation, see
Application Note AN554, “Software Implementation of
2
I
C™ Bus Master”.
TABLE 10-3:
REGISTERS ASSOCIATED WITH I
Address
Name
Bit 7
Bit 6
0Bh, 8Bh,
INTCON
GIE
PEIE
10Bh,18Bh
(1)
0Ch
PIR1
—
ADIF
(1)
8Ch
PIE1
—
ADIE
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
93h
SSPADD
Synchronous Serial Port (I
14h
SSPCON
WCOL
SSPOV
(2)
(2)
94h
SSPSTAT
SMP
CKE
86h
TRISB
PORTB Data Direction Register
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI™ mode.
Note 1:
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
2
2:
Maintain these bits clear in I
C™ mode.
 2005 Microchip Technology Inc.
10.3.3
MULTI-MASTER MODE OPERATION
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the Start and Stop conditions
allows the determination of when the bus is free. The
Stop (P) and Start (S) bits are cleared from a Reset, or
when the SSP module is disabled. The Stop (P) and
2
C bus
Start (S) bits will toggle based on the Start and Stop
conditions. Control of the I
bit P (SSPSTAT<4>) is set, or the bus is Idle and both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
Stop condition occurs.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected out-
put level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB<4,1>). There are two stages
C module.
where this arbitration can be lost:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave device
continues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to retransfer the
data at a later time.
For more information on Multi-Master mode operation,
see Application Note AN578, “Use of the SSP Module
2
in the of I
C™ Multi-Master Environment”.
2
C™ OPERATION
Bit 5
Bit 4
Bit 3
Bit 2
TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
2
C mode) Address Register
SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0
D/A
P
S
R/W
PIC16F87/88
2
C bus may be taken when
Value on
Value on
Bit 1
Bit 0
all other
POR, BOR
Resets
RBIF
0000 000x 0000 000u
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
UA
BF
0000 0000 0000 0000
1111 1111 1111 1111
DS30487C-page 95

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