PIC16F914 Microchip Technology Inc., PIC16F914 Datasheet

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PIC16F914

Manufacturer Part Number
PIC16F914
Description
Manufacturer
Microchip Technology Inc.
Datasheet
PIC16F913/914/916/917/946
Data Sheet
28/40/44/64-Pin Flash-Based,
8-Bit CMOS Microcontrollers with
LCD Driver and nanoWatt Technology
© 2007 Microchip Technology Inc.
DS41250F

Related parts for PIC16F914

PIC16F914 Summary of contents

Page 1

... PIC16F913/914/916/917/946 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology © 2007 Microchip Technology Inc. 28/40/44/64-Pin Flash-Based, Data Sheet DS41250F ...

Page 2

... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified logo, microID, MPLAB, PIC MCUs and dsPIC DSCs code hopping ® ® ® © 2007 Microchip Technology Inc. ...

Page 3

... Multiplexed Master Clear with pull-up/input pin • Programmable code protection • High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Low-Power Features: • Standby Current: - <100 nA @ 2.0V, typical • Operating Current μ ...

Page 4

... PIC16F917 8K/14K 352 PIC16F946 8K/14K 336 Note 1: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays. Pin Diagrams – PIC16F914/917, 40-Pin 40-pin PDIP RE3/MCLR/V PP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/V -/COM2 REF RA3/AN3/C1+/V ...

Page 5

... TABLE 1: PIC16F914/917 40-PIN SUMMARY I/O Pin A/D LCD Comparators RA0 2 AN0 SEG12 C1- RA1 3 AN1 SEG7 C2- RA2 4 AN2/V - COM2 C2+ REF RA3 5 SEG15 C1+ AN3/V + REF RA4 6 SEG4 C1OUT RA5 7 AN4 SEG5 C2OUT RA6 14 — — — RA7 13 — — — RB0 33 — SEG0 — RB1 34 — ...

Page 6

... PIC16F913/916 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 RC7/RX/DT/SDI/SDA/SEG8 © 2007 Microchip Technology Inc. ...

Page 7

... Note 1: Pull-up enabled only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Timers CCP AUSART SSP — — — — — — — — — — — — ...

Page 8

... ICSPDAT/ICDDAT — — — — — — — — — — — — — — — — — — — — — — — — (1) — Y MCLR/V PP — — — — — — © 2007 Microchip Technology Inc. ...

Page 9

... Pin Diagrams – PIC16F914/917, 44-Pin 44-pin TQFP RC7/RX/DT/SDI/SDA/SEG8 1 RD4/SEG17 2 RD5/SEG18 3 RD6/SEG19 4 RD7/SEG20 RB0/SEG0/INT 8 RB1/SEG1 9 RB2/SEG2 10 RB3/SEG3 11 44-pin QFN RC7/RX/DT/SDI/SDA/SEG8 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 NC 33 RC0/VLCD1 32 RA6/OSC2/CLKOUT/T1OSO 31 RA7/OSC1/CLKIN/T1OSI PIC16F914/917 RE2/AN7/SEG23 27 RE1/AN6/SEG22 26 RE0/AN5/SEG21 ...

Page 10

... PIC16F913/914/916/917/946 TABLE 4: PIC16F914/917 44-PIN (TQFP) SUMMARY I/O Pin A/D LCD Comparators RA0 19 AN0 SEG12 C1- RA1 20 AN1 SEG7 C2- RA2 21 AN2/V - COM2 C2+ REF RA3 22 AN3/V + SEG15 C1+ REF RA4 23 — SEG4 C1OUT RA5 24 AN4 SEG5 C2OUT RA6 31 — — — RA7 30 — — — RB0 8 — ...

Page 11

... TABLE 5: PIC16F914/917 44-PIN (QFN) SUMMARY I/O Pin A/D LCD Comparators RA0 19 AN0 SEG12 C1- RA1 20 AN1 SEG7 C2- RA2 21 AN2/V - COM2 C2+ REF RA3 22 AN3/V + SEG15 C1+ REF RA4 23 — SEG4 C1OUT RA5 24 AN4 SEG5 C2OUT RA6 33 — — — RA7 32 — — — RB0 9 — SEG0 — ...

Page 12

... RB1/SEG1 DS41250F-page PIC16F946 RF7/SEG31 47 RF6/SEG30 46 RF5/SEG29 45 RF4/SEG28 44 RE7/SEG27 43 RE6/SEG26 RE5/SEG25 RA6/OSC2/CLKOUT/T1OSO 39 RA7/OSC1/CLKIN/T1OSI RE4/SEG24 36 RE3/MCLR RE2/AN7/SEG23 34 RE1/AN6/SEG22 RE0/AN5/SEG21 33 © 2007 Microchip Technology Inc. ...

Page 13

... SEG32 — RF1 12 — SEG33 — RF2 13 — SEG34 — Note 1: Pull-up enabled only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Timers CCP AUSART SSP — — — — — — — — — — — — ...

Page 14

... AV DD — — — — — — — — — — — — — — — — — — © 2007 Microchip Technology Inc. ...

Page 15

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 DS41250F-page 13 ...

Page 16

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 14 © 2007 Microchip Technology Inc. ...

Page 17

... The PIC16F91X/946 devices are covered by this data sheet. They are available in 28/40/44/64-pin packages. Figure 1-1 shows a block diagram of the PIC16F913/916 device, Figure 1-2 shows a block diagram of the PIC16F914/917 device, and Figure 1-3 shows a block diagram of the PIC16F946 device. Table 1-1 shows the pinout descriptions. FIGURE 1-1: ...

Page 18

... PIC16F913/914/916/917/946 FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM Configuration 13 Program Counter Flash 4K/ Program 8-Level Stack (13-bit) Memory Program 14 Program Memory Read Bus Instruction Reg Direct Addr 8 Power-up Instruction Oscillator Decode and Control Start-up Timer OSC1/CLKIN Power-on Timing OSC2/CLKOUT Watchdog Generation Brown-out Internal Oscillator ...

Page 19

... Watchdog Timer Timing OSC2/CLKOUT Generation Brown-out Reset Internal Oscillator Block Timer0 Timer1 Comparators CCP1 CCP2 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 INT 8 Data Bus RAM 336 x 8 bytes File Registers RAM Addr 9 (PMR) Addr MUX Indirect 7 8 Addr FSR Reg ...

Page 20

... RB0 INT SEG0 Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...

Page 21

... T1CKI CCP1 SEG10 Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...

Page 22

... MCLR V PP Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...

Page 23

... Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...

Page 24

... Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...

Page 25

... PIC16F916/ 917 and PIC16F946 (0000h-1FFFh). Accessing a location above the memory boundaries for the PIC16F913 and PIC16F914 will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h. ...

Page 26

... The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS41250F-page 24 © 2007 Microchip Technology Inc. ...

Page 27

... Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register the PIC16F913, unimplemented data memory locations, read as ‘0’. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 File File Address Address (1) (1) 80h Indirect addr. 100h ...

Page 28

... Register 80 Bytes 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register the PIC16F914, unimplemented data memory locations, read as ‘0’. DS41250F-page 26 File File Address Address (1) (1) 80h Indirect addr. 100h TMR0 101h ...

Page 29

... General Register Purpose Register 80 Bytes 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 File File Address Address (1) (1) 80h Indirect addr. 100h TMR0 101h 82h PCL ...

Page 30

... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916. 3: PIC16F946 only, forced to ‘0’ on PIC16F91X. DS41250F-page 28 Bit 5 ...

Page 31

... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: PIC16F946 only, forced ‘0’ on PIC16F91X. 3: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916. 4: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.2 “Oscillator Control”. ...

Page 32

... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: PIC16F914/917 and PIC16F946 only. 3: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. DS41250F-page 30 Bit 5 ...

Page 33

... Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. 3: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0CS ...

Page 34

... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (ADDWF, ADDLW, SUBLW, SUBWF instructions) Status bits (see Section 17.0 R/W-x R/W-x R/W-x (1) ( bit Bit is unknown (1) (1) © 2007 Microchip Technology Inc. ...

Page 35

... Bit Value 000 001 010 011 100 101 110 111 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 6.3 “Timer1 Prescaler”. R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘ ...

Page 36

... GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1) (2) INTE RBIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-x INTF RBIF bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 37

... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...

Page 38

... Enables LVD Interrupt 0 = Disables LVD Interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note 1: PIC16F914/PIC16F917/PIC16F946 only. DS41250F-page 36 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 U-0 R/W-0 LCDIE — ...

Page 39

... No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software The TMR1 register did not overflow © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...

Page 40

... A TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode Note 1: PIC16F914/PIC16F917/PIC16F946 only. DS41250F-page 38 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...

Page 41

... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> the Configuration Word register for this bit to control the BOR. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 U-0 U-0 SBOREN — ...

Page 42

... ORG 900h SUB1_P1 : : RETURN RETLW and RETFIE instruc- Therefore, manipulation of the CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) © 2007 Microchip Technology Inc. ...

Page 43

... Direct Addressing From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, see Figures 2-3 and 2-4. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 2-2: MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE 0 IRP Bank Select ...

Page 44

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 42 © 2007 Microchip Technology Inc. ...

Page 45

... PORTG and TRISG Note 1: PIC16F914/917 and PIC16F946 only. 2: PIC16F946 only PORTA, PORTB, PORTC and RE3/MCLR/V implemented on all devices. PORTD and RE<2:0> (PORTE) are implemented only on the PIC16F914/917 and PIC16F946. RE<7:4> (PORTE), PORTF and PORTG are implemented only on the PIC16F946. REGISTER 3-1: ANSEL: ANALOG SELECT REGISTER ...

Page 46

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared INITIALIZING PORTA ; ;Init PORTA ; ;Set RA<2:0> to ;digital I/O ;Make all PORTA digital I/O ;Set RA<7:4> as inputs ;and set RA<3:0> as outputs R/W-x R/W-x RA1 RA0 bit Bit is unknown R/W-1 R/W-1 TRISA1 TRISA0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 47

... FIGURE 3-1: BLOCK DIAGRAM OF RA0 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA SEG12 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Analog Input or SE12 and LCDEN SE12 and LCDEN SE12 and LCDEN To A/D Converter and Comparator V DD I/O Pin ...

Page 48

... Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA SEG7 DS41250F-page Analog Input or SE7 and LCDEN SE7 and LCDEN SE7 and LCDEN To A/D Converter and Comparator V DD I/O Pin V SS TTL Input Buffer © 2007 Microchip Technology Inc. ...

Page 49

... LCD FIGURE 3-3: BLOCK DIAGRAM OF RA2 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA COM2 To A/D Converter and Comparator To A/D Module V © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 LMUX<1:0> LCDEN and LMUX<1:0> LCDEN and LMUX<1:0> Input REF V DD I/O Pin V ...

Page 50

... WR TRISA CK TRIS Latch RD TRISA RD PORTA (1) COM3 To A/D Converter and Comparator To A/D Module V Note 1: PIC16F913/916 only. 2: For the PIC16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11). For the PIC16F914/917 and PIC16F946, the LCDMODE_EN = LCDEN and SE15. DS41250F-page Analog Input or LCDMODE_EN (2) LCDMODE_EN (2) LCDMODE_EN ...

Page 51

... BLOCK DIAGRAM OF RA4 CM<2:0> = 110 or 101 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA T0CKI SEG4 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 C1OUT SE4 and LCDEN SE4 and LCDEN Schmitt Trigger SE4 and LCDEN V DD ...

Page 52

... D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA To SS Input SEG5 To A/D Converter DS41250F-page 50 C2OUT Analog Input or SE5 and LCDEN Input Buffer SE5 and LCDEN SE5 and LCDEN V DD I/O Pin V SS TTL © 2007 Microchip Technology Inc. ...

Page 53

... CLKOUT (F Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch F = 00x, 010 OSC or T1OSCEN RD TRISA RD PORTA © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 F = 1x1 OSC From OSC1 /4) OSC 00x, 010 OSC or T1OSCEN Input Buffer Oscillator Circuit V DD I/O Pin ...

Page 54

... LMUX0 0001 0011 0001 0011 SE0 0000 0000 uuuu uuuu SE8 0000 0000 uuuu uuuu RA0 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 TMR1ON 0000 0000 uuuu uuuu TRISA0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...

Page 55

... MOVLW 0FFh ;Set RB<7:0> as inputs MOVWF TRISB ; © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.4 Additional PORTB Pin Functions RB<7:6> are used as data and clock signals, respectively, for both serial programming and the in-circuit debugger features on the device. Also, RB0 can be configured as an external interrupt input. ...

Page 56

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 U-0 IOCB4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x RB1 RB0 bit Bit is unknown R/W-1 R/W-1 TRISB1 TRISB0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 57

... WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global RBPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISx<7:0> = 0). © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 R/W-1 R/W-1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘ ...

Page 58

... Figure 3-9 shows the diagram for this pin. The RB3 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD SE<3:0> SE<3:0> and LCDEN TTL Input Buffer SE<3:0> and LCDEN Schmitt Trigger SE0 and LCDEN Weak P Pull-up I/O Pin V SS © 2007 Microchip Technology Inc. ...

Page 59

... RBPU Data Bus WR PORTB WR TRISB RD TRISB RD PORTB WR IOC RD IOC Set RBIF Interrupt-on Change From other RB<7:4> pins R Write ‘0’ to RBIF COM0 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 LCDEN WPUB<4> Data Latch TRIS Latch LCDEN LCDEN LCDEN ...

Page 60

... Write ‘0’ to RBIF COM1 DS41250F-page 58 ≠ LCDEN and LMUX<1:0> LCDEN and LMUX<1:0> LCDEN and ≠ LMUX<1:0> 00 ≠ LCDEN and LMUX<1:0> Weak P Pull-up I/O Pin V SS ≠ 00 TTL Input Buffer PORTB © 2007 Microchip Technology Inc. ...

Page 61

... WR PORTB WR TRISB RD TRISB RD PORTB WR IOC RD IOC Set RBIF Interrupt-on Change From other RB<7:4> pins R Write ‘0’ to RBIF ICSPCLK SEG14 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Data Latch D Q SE14 and LCDEN CK TRIS Latch Program Mode/ICD Schmitt Trigger ...

Page 62

... TRIS Latch 0 1 SE13 and LCDEN Program Mode/ICD Schmitt Trigger Program Mode or ICD Mode or (SE13 and LCDEN) SE13 and LCDEN V DD Weak P Pull- I/O Pin V SS TTL Input Buffer PORTB © 2007 Microchip Technology Inc. ...

Page 63

... Shaded cells are not used by PORTB. Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. 2: Configuration Word register bit DEBUG <12> is also associated with PORTB. See Register 16-1 for more details. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 64

... Bit is cleared R/W-1 R/W-1 R/W-1 TRISC4 TRISC3 TRISC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared INITIALIZING PORTC ; ;Init PORTC ; ;Set RC<7:0> as inputs ; ; ;Disable VLCD<3:1> ;inputs on RC<2:0> R/W-x R/W-x RC1 RC0 bit Bit is unknown R/W-1 R/W-1 TRISC1 TRISC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 65

... Q WR TRISC Q CK TRIS Latch RD TRISC RD PORTC VLCD1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.5.1.3 RC2/VLCD3 Figure 3-16 shows the diagram for this pin. The RC2 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the LCD bias voltage ≠ ...

Page 66

... Data Bus PORTC Q CK Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC VLCD3 DS41250F-page 64 ≠ (VLCDEN and LMUX<1:0> 00) ≠ (LCDEN and LMUX<1:0> 00) VLCDEN Schmitt Trigger LCDEN V DD I/O Pin V SS Schmitt Trigger V DD I/O Pin V SS © 2007 Microchip Technology Inc. ...

Page 67

... LCD FIGURE 3-17: BLOCK DIAGRAM OF RC3 Data Bus PORTC Q CK Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC SEG6 and LCDEN © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 SE6 and LCDEN Schmitt Trigger SE6 and LCDEN V DD I/O Pin V SS DS41250F-page 65 ...

Page 68

... BLOCK DIAGRAM OF RC4 PORT/SDO Select Data Bus PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC RD PORTC Timer1 Gate SEG11 DS41250F-page 66 SDO 0 1 SE11 and LCDEN SE11 and LCDEN V DD I/O Pin V SS Schmitt Trigger © 2007 Microchip Technology Inc. ...

Page 69

... Select) and CCPMX CCP1 Data Out Data Bus PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC SE10 and LCDEN RD PORTC Timer1 Clock Input SEG10 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 0 1 Schmitt Trigger SE10 and LCDEN V DD I/O Pin V SS DS41250F-page 67 ...

Page 70

... If all three data output sources are enabled, the following priority order will be used: • USART data (highest) • SSP data • PORT data (lowest) DS41250F-page 68 (1) SE9 and LCDEN SE9 and LCDEN V DD I/O Pin V SS Schmitt Trigger © 2007 Microchip Technology Inc. ...

Page 71

... SE8 and LCDEN SEG8 Note 1: If all three data output sources are enabled, the following priority order will be used: • USART data (highest) • SSP data • PORT data (lowest) © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 0 1 SE8 and LCDEN Schmitt Trigger ...

Page 72

... SE0 0000 0000 uuuu uuuu SE8 0000 0000 uuuu uuuu RC0 xxxx xxxx uuuu uuuu RX9D 0000 000x 0000 000x SSPM0 0000 0000 0000 0000 TMR1ON 0000 0000 uuuu uuuu TRISC0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...

Page 73

... PORTD and TRISD Registers PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. PORTD is only available on the PIC16F914/917 and PIC16F946. REGISTER 3-10: PORTD: PORTD REGISTER R/W-x R/W-x R/W-x RD7 RD6 RD5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...

Page 74

... I/O • an analog output for the LCD 3.6.1.8 RD7/SEG20 Figure 3-25 shows the diagram for this pin. The RD7 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD © 2007 Microchip Technology Inc. ...

Page 75

... COM3 FIGURE 3-23: BLOCK DIAGRAM OF RD1 Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 LCDEN and LMUX<1:0> LCDEN and LMUX<1:0> Schmitt Trigger V DD I/O Pin V SS Schmitt Trigger V DD RD1 Pin V ...

Page 76

... CCP2 Input FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3> Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD SE<20:16> and LCDEN SEG<20:16> DS41250F-page Schmitt Trigger SE<20:16> and LCDEN Schmitt Trigger V DD I/O Pin I/O Pin V SS © 2007 Microchip Technology Inc. ...

Page 77

... RD7 RD6 RD5 (1) TRISD TRISD7 TRISD6 TRISD5 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Note 1: PIC16F914/917 and PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 CCP2Y CCP2M3 CCP2M2 CCP2M1 VLCDEN ...

Page 78

... PORTE is a 1-bit, 4-bit or 8-bit port with Schmitt Trigger input buffers. RE<7:4, 2:0> are individually configured as inputs or outputs and RE3 is only available as an input if MCLRE is ‘0’ in Configuration Word (Register 16-1). RE<2:0> are only available on the PIC16F914/917 and PIC16F946. RE<7:4> are only available on the PIC16F946. REGISTER 3-12: ...

Page 79

... LCD 3.7.1.8 RE7/SEG27 Figure 3-28 shows the diagram for this pin. The RE7/SEG27 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD Note 1: Pin is available on the PIC16F914/917 and PIC16F946 only. 2: Pin is available on the PIC16F946 only. (2) (2) DS41250F-page 77 ...

Page 80

... PIC16F913/914/916/917/946 FIGURE 3-26: BLOCK DIAGRAM OF RE<2:0> (PIC16F914/917 AND PIC16F946 ONLY) Data Bus PORTE CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE RD PORTE SEG<23:21> and LCDEN SEG<23:21> AN<7:5> FIGURE 3-27: BLOCK DIAGRAM OF RE3 MCLR circuit Programming mode Data Bus RD TRISE RD PORTE DS41250F-page 78 Analog Mode or SEG< ...

Page 81

... FIGURE 3-28: BLOCK DIAGRAM OF RE<7:4> (PIC16F946 ONLY) Data Bus PORTE CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE RD PORTE SEG<27:24> and LCDEN SEG<27:24> AN<7:5> © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Analog Mode or SEG<27:24> and LCDEN Schmitt Trigger V DD I/O Pin V SS DS41250F-page 79 ...

Page 82

... TRISE5 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. 2: PIC16F914/917 and PIC16F946 only. 3: PIC16F946 only. 4: Bit is read-only; TRISE = 1 always. DS41250F-page 80 Bit 4 Bit 3 ...

Page 83

... Value at POR ‘1’ = Bit is set bit 7-0 TRISF<7:0>: PORTF Tri-State Control bits 1 = PORTF pin configured as an input (tri-stated PORTF pin configured as an output Note 1: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 3-6: BANKSEL PORTF CLRF PORTF BANKSEL TRISF MOVLW 0FFh ...

Page 84

... I/O • an analog output for the LCD 3.8.1.8 RF7/SEG31 Figure 3-29 shows the diagram for this pin. The RF7 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD © 2007 Microchip Technology Inc. ...

Page 85

... RF6 RF5 (1) TRISF TRISF7 TRISF6 TRISF5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF. Note 1: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 SE<35:28> and LCDEN Schmitt Trigger SE<35:28> and LCDEN Bit 4 Bit 3 Bit 2 Bit 1 VLCDEN ...

Page 86

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 R/W-1 TRISG4 TRISG3 TRISG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared INITIALIZING PORTG ; ;Init PORTG ; ;Set RG<5:0> as inputs ; R/W-x R/W-x RG1 RG0 bit Bit is unknown R/W-1 R/W-1 TRISG1 TRISG0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 87

... Data Latch TRISG CK Q TRIS Latch RD TRISG RD PORTG SEG<41:36> © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.9.1.4 RG3/SEG39 Figure 3-30 shows the diagram for this pin. The RG3 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.5 RG4/SEG40 Figure 3-30 shows the diagram for this pin ...

Page 88

... SE41 RG4 RG3 RG2 RG1 TRISG4 TRISG3 TRISG2 TRISG1 (1) Value on all Value on Bit 0 other POR, BOR Resets LMUX0 0001 0011 0001 0011 SE32 0000 0000 uuuu uuuu SE40 ---- --00 ---- --uu RG0 --xx xxxx --uu uuuu TRISG0 --11 1111 --11 1111 © 2007 Microchip Technology Inc. ...

Page 89

... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...

Page 90

... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. DS41250F-page 88 R/W-0 R-1 R-0 (1) IRCF0 OSTS HTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R/W-0 LTS SCS bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 91

... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.4 External Clock Modes 4 ...

Page 92

... Oscillator Design” (DS00849) ® Oscillator Analysis and Design” (DS00943) (DS00949) CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic ( Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode F P © 2007 Microchip Technology Inc. ) ...

Page 93

... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...

Page 94

... Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 95

... Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING ...

Page 96

... HFINTOSC LFINTOSC ≠ IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC = 0 IRCF <2:0> System Clock DS41250F-page 94 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled ≠ 0 Running Running Running © 2007 Microchip Technology Inc. ...

Page 97

... Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.4.1 “Oscillator Start-up Timer (OST)” ...

Page 98

... FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 4-7: TWO-SPEED START-UP HFINTOSC T T OST OSC1 1022 1023 0 1 OSC2 Program Counter System Clock DS41250F-page © 2007 Microchip Technology Inc. ...

Page 99

... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...

Page 100

... Test Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 — — RBIF 0000 000x 0000 000x SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu CCP2IE 0000 -0-0 0000 -0-0 CCP2IF 0000 -0-0 0000 -0-0 TMR1ON 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...

Page 101

... T0SE, T0CS, PSA, PS<2:0> are bits in the Option register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...

Page 102

... T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements Section 19.0 “Electrical Specifications” © 2007 Microchip Technology Inc. as shown in ...

Page 103

... RBPU INTEDG T0CS TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...

Page 104

... T1CKI pin TMR1ON To C2 Comparator Module Timer1 Clock ( TMR1L 1 To LCD Module T1SYNC ( Prescaler OSC Internal 0 Clock T1CKPS<1:0> TMR1CS SYNCC2OUT TMR1CS 0 1 TMR1GE T1GINV Synchronized clock input (3) Synchronize det 2 T1G 1 (4) 0 T1GSS © 2007 Microchip Technology Inc. ...

Page 105

... TRISA7 and TRISA6 bits read as ‘1’. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized ...

Page 106

... Clock Source for LCD Module The Timer1 oscillator can be used to provide a clock for the LCD module. This clock may be configured to remain running during Sleep. For more information, see Section 10.0 “Liquid Crys- tal Display (LCD) Driver Module”. © 2007 Microchip Technology Inc. ...

Page 107

... Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘ ...

Page 108

... Bit 0 all other POR, BOR Resets C2SYNC ---- --10 ---- --10 RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 0000 uuuu uuuu © 2007 Microchip Technology Inc. ...

Page 109

... F /4 OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...

Page 110

... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 © 2007 Microchip Technology Inc. ...

Page 111

... Timer1 gate (count enable) • Output synchronization to Timer1 clock input • Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 8.1 Comparator Overview A comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output ...

Page 112

... RD CMCON0 D Q Q3*RD CMCON0 EN CL Reset OSC C2SYNC D Q Timer1 (1) clock source CMCON0 D Q Q3*RD CMCON0 EN CL Reset OSC To C1OUT pin To Data Bus Set C1IF bit ). To SYNCC2OUT 0 To C2OUT pin 1 To Data Bus Set C2IF bit ). © 2007 Microchip Technology Inc. ...

Page 113

... Analog Voltage Threshold Voltage T © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog ...

Page 114

... TRIS bit set to ‘1’ to disable the digital output driver. Pins denoted as “D” should have the corresponding TRIS bit set to ‘0’ to enable the digital output driver. Note: Comparator interrupts should be disabled during a Comparator mode change to prevent unintended interrupts. DS41250F-page 112 © 2007 Microchip Technology Inc. ...

Page 115

... IN I/O C1IN C2IN C2IN+ Legend Analog Input, ports always reads ‘0’ I/O = Normal port I/O © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Two Independent Comparators CM<2:0> = 100 A C1IN- Off (Read as ‘0’) A C1IN+ A C2IN- Off (Read as ‘0’) A C2IN+ One Independent Comparator with Reference Option CM< ...

Page 116

... See Figures 8-6 and 8-7 b) Clear the CxIF interrupt flag. A persistent mismatch condition will preclude clearing the CxIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CxIF bit to be cleared. all writes include a read © 2007 Microchip Technology Inc. ...

Page 117

... Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 8.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep ...

Page 118

... Two comparators with outputs and common reference 111 = Comparators off. CxIN pins are configured as digital I/O DS41250F-page 116 R/W-0 R/W-0 R/W-0 C1INV CIS CM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - R/W-0 R/W-0 CM1 CM0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 119

... C2SYNC: Comparator C2 Output Synchronization bit 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-3. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 8.9 Synchronizing Comparator C2 Output to Timer1 The output of Comparator C2 can be synchronized with Timer1 by setting the C2SYNC bit of the CMCON1 register ...

Page 120

... (VR<3:0>/32 OUTPUT VOLTAGE REF = (VR<3:0>/24) × × (VR<3:0> V /32 / cannot be realized due module current. REF derived and DD output changes with fluctuations in REF R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown . © 2007 Microchip Technology Inc. ...

Page 121

... TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 VRCON VREN — VRR Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 16 Stages VREN VR<3:0> = 0000 VRR Note 1: Care should be taken to ensure V within the comparator common mode input range. See Section 19.0 “ ...

Page 122

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 120 © 2007 Microchip Technology Inc. ...

Page 123

... Multiplier x4 SYNC 1 SPBRG BRGH x © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The AUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length Synchronous • Address detection in 9-bit mode (AUSART) • ...

Page 124

... DS41250F-page 122 SPEN MSb Data Stop Recovery F OSC ÷ x16 x64 FERR CREN OERR RSR Register LSb • • • ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2007 Microchip Technology Inc. ...

Page 125

... TX/CK I/O pin as an output. The LCD SEG9 function must be disabled by clearing the SE9 bit of the LCDSE1 register, if the TX/CK pin is shared with the LCD peripheral. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, ...

Page 126

... TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. © 2007 Microchip Technology Inc. ...

Page 127

... TRISC7 TRISC6 TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF VLCDEN ...

Page 128

... PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. © 2007 Microchip Technology Inc. ...

Page 129

... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...

Page 130

... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Start bit Stop bit 7/8 bit © 2007 Microchip Technology Inc. ...

Page 131

... SSPOV SSPEN TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF VLCDEN CS1 CS0 ...

Page 132

... TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS41250F-page 130 R/W-0 U-0 R/W-0 (1) SYNC — BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-1 R/W-0 TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 133

... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...

Page 134

... Baud Rate Formula F /[64 (n+1)] OSC F /[16 (n+1)] OSC F /[4 (n+1)] OSC Value on Value on Bit 0 all other POR, BOR Resets RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 © 2007 Microchip Technology Inc. ...

Page 135

... Microchip Technology Inc. PIC16F913/914/916/917/946 SYNC = 0, BRGH = 18.432 MHz F = 11.0592 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — — — — ...

Page 136

... MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — 300 0.16 207 103 1202 0. 2404 0. — — — 11 10417 0.00 5 — — — — — — — — — — — — © 2007 Microchip Technology Inc. ...

Page 137

... One clock cycle is generated for each data bit. Only as many clock cycles are gener- ated as there are data bits. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.3.1.2 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin ...

Page 138

... TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 SSPM0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 © 2007 Microchip Technology Inc. ...

Page 139

... CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.3.1.7 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When ...

Page 140

... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000X 0000 000X SSPM0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 © 2007 Microchip Technology Inc. ...

Page 141

... CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...

Page 142

... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000X 0000 000X SSPM0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 © 2007 Microchip Technology Inc. ...

Page 143

... Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.4.2 SYNCHRONOUS TRANSMIT DURING SLEEP ...

Page 144

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 142 © 2007 Microchip Technology Inc. ...

Page 145

... LCD panel. In the PIC16F913/916 devices, the module drives the panels four commons and segments. In the PIC16F914/917 devices, the module drives the panels four commons and segments. In the PIC16F946 device, the module drives the panels four commons and segments ...

Page 146

... Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. 2: SEG<23:0> on PIC16F914/917, SEG<15:0> on PIC16F913/916. 3: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays. DS41250F-page 144 SEG< ...

Page 147

... On PIC16F913/916 devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 R/W-0 R/W-0 VLCDEN CS1 CS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Maximum Number of Pixels PIC16F913/916 PIC16F914/917 ( R/W-1 R/W-1 LMUX1 LMUX0 ...

Page 148

... LP<3:0>: LCD Prescaler Select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 DS41250F-page 146 R-0 R/W-0 R/W-0 WA LP3 LP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/W-0 R/W-0 LP1 LP0 bit Bit is unknown ...

Page 149

... SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear) © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R/W-0 SEn SEn SEn U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x ...

Page 150

... Connections for External R-ladder Static Bias 1/2 Bias 10 kΩ 1/3 Bias 10 kΩ and 1/2 V and 1 2 Static 1/2 Bias 1/3 Bias Bias — 1 — 1 © 2007 Microchip Technology Inc. ...

Page 151

... COM3 Driver COM2 Driver COM1 Driver 1/4 11 Note 1: RA3 for PIC16F913/916, RD0 for PIC16F914/917 and PIC16F946 10.5 Segment Enables The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin’s alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to ‘ ...

Page 152

... PIC16F913/914/916/917/946 FIGURE 10-3: LCD CLOCK GENERATION F ÷8192 OSC T1OSC 32 kHz ÷32 Crystal Osc. LFINTOSC ÷32 Nominal = 31 kHz CS<1:0> (LCDCON<3:2>) DS41250F-page 150 Static ÷4 1/2 ÷2 4-bit Prog Presc 1/3, 1/4 LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) © 2007 Microchip Technology Inc. ÷ Ring Counter LMUX<1:0> (LCDCON<1:0>) ...

Page 153

... FIGURE 10-4: LCD SEGMENT MAPPING WORKSHEET (SHEET © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 DS41250F-page 151 ...

Page 154

... PIC16F913/914/916/917/946 FIGURE 10-5: LCD SEGMENT MAPPING WORKSHEET (SHEET DS41250F-page 152 © 2007 Microchip Technology Inc. ...

Page 155

... FIGURE 10-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary ...

Page 156

... TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41250F-page 154 COM0 COM1 SEG0 SEG1 1 Frame © 2007 Microchip Technology Inc. ...

Page 157

... FIGURE 10-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 SEG0 SEG1 2 Frames ...

Page 158

... DS41250F-page 156 COM0 COM1 SEG0 SEG1 1 Frame © 2007 Microchip Technology Inc. ...

Page 159

... FIGURE 10-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 SEG0 SEG1 2 Frames ...

Page 160

... COM0-SEG0 COM0-SEG1 DS41250F-page 158 COM0 COM1 COM2 SEG0 SEG2 SEG1 Frame © 2007 Microchip Technology Inc. ...

Page 161

... FIGURE 10-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 COM2 SEG0 SEG1 ...

Page 162

... SEG1 Frame © 2007 Microchip Technology Inc. ...

Page 163

... FIGURE 10-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 COM2 SEG0 SEG1 ...

Page 164

... © 2007 Microchip Technology Inc. ...

Page 165

... FIGURE 10-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames ...

Page 166

... Frame Boundary /2 CY /4) – ns) FRAME CY /4) – ns) FRAME CY Controller Accesses Next Frame Data FINT Frame Boundary © 2007 Microchip Technology Inc. ...

Page 167

... Microchip Technology Inc. PIC16F913/914/916/917/946 Table 10-5 shows the status of the LCD module during a Sleep while using each of the three available clock ...

Page 168

... PIC16F913/914/916/917/946 FIGURE 10-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 COM0 COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution DS41250F-page 166 Wake-up © 2007 Microchip Technology Inc ...

Page 169

... Enable the LCD module by setting bit LCDEN of the LCDCON register. 10.12 Disabling the LCD Module To disable the LCD module, write all ‘0’s to the LCDCON register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 10.13 LCD Current Consumption When using the LCD module the current consumption consists of the following three factors: 1 ...

Page 170

... SE14 SE13 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the LCD module. Note 1: These pins may be configured as port pins, depending on the oscillator mode selected. 2: PIC16F914/917 and PIC16F946 only. 3: PIC16F946 only. DS41250F-page 168 Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 171

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the LCD module. Note 1: These pins may be configured as port pins, depending on the oscillator mode selected. 2: PIC16F914/917 and PIC16F946 only. 3: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 ...

Page 172

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 170 © 2007 Microchip Technology Inc. ...

Page 173

... PLVD OPERATION V DD PLVD Trip Point LVDIF Set by Hardware © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The PLVD module includes the following capabilities: • Eight programmable trip points • Interrupt on falling V • Stable reference indication • Operation during Sleep A Block diagram of the PLVD module is shown in Figure 11-1 ...

Page 174

... LVDIE and PEIE bits are set, the device will wake from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine upon completion of the first instruction after waking from Sleep. © 2007 Microchip Technology Inc. ...

Page 175

... IRVST PIE2 OSFIE C2IE C1IE PIR2 OSFIF C2IF C1IF Legend unknown unimplemented read as ‘0’. Shaded cells are not used by the PLVD module. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 U-0 R/W-1 (1) LVDEN — LVDL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 176

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 174 © 2007 Microchip Technology Inc. ...

Page 177

... RA5/AN4 RE0/AN5 RE1/AN6 RE2/AN7 CHS Note 1: These channels are only available on PIC16F914/917 and PIC16F946 devices. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of (ADC) allows a conversion ...

Page 178

... Section 19.0 “Electrical Specifications” for more information. Table 12-1 gives examples of appropriate ADC clock selections. Note: Unless using the F , any changes in the RC system clock frequency will change the ADC clock frequency, adversely affect the ADC result. © 2007 Microchip Technology Inc periods AD specification AD which may ...

Page 179

... Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 12.1.5 “Interrupts” for more information. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V ...

Page 180

... ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. See Section 15.0 “Capture/Compare/PWM (CCP) Module” for more information. ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 RC clock source is selected, the RC © 2007 Microchip Technology Inc. ...

Page 181

... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 12.3 “A/D Acquisition Requirements”. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 12-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ...

Page 182

... ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: Not available on 28-pin devices. DS41250F-page 180 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 183

... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — ...

Page 184

... ADRES4 ADRES3 ADRES2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x ADRES3 ADRES2 bit Bit is unknown R/W-x R/W-x — — bit Bit is unknown R/W-x R/W-x ADRES9 ADRES8 bit Bit is unknown R/W-x R/W-x ADRES1 ADRES0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 185

... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC) ...

Page 186

... LEAKAGE ( 0.6V T Full-Scale Range 1 LSB ideal Zero-Scale REF Transition Sampling Switch SS Rss HOLD REF Sampling Switch (kΩ) 1 LSB ideal Full-Scale Transition Analog Input Voltage © 2007 Microchip Technology Inc. ...

Page 187

... TRISA5 TRISB TRISB7 TRISB6 TRISB5 TRISE TRISE7 TRISE6 TRISE5 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — ...

Page 188

... PIC16F913/914/916/917/946 NOTES: DS41250F-page 186 © 2007 Microchip Technology Inc. ...

Page 189

... EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 13.1 EEADRL and EEADRH Registers The EEADRL and EEADRH registers can address maximum of 256 bytes of data EEPROM maximum of 8K words of program Flash ...

Page 190

... EEDATH4 EEDATH3 EEDATH2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 EEDATL1 EEDATL0 bit Bit is unknown R/W-0 R/W-0 EEADRL1 EEADRL0 bit Bit is unknown R/W-0 R/W-0 EEDATH1 EEDATH0 bit Bit is unknown R/W-0 R/W-0 EEDATH1 EEDATH0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 191

... Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘ ...

Page 192

... DATA ;memory BSF EECON1,WREN ;Enable writes BCF INTCON,GIE ;Disable INTs. MOVLW 55h ; MOVWF EECON2 ;Write 55h MOVLW AAh ; MOVWF EECON2 ;Write AAh BSF EECON1,WR ;Set WR bit to ;begin write BSF INTCON,GIE ;Enable INTs. BCF EECON1,WREN ;Disable writes © 2007 Microchip Technology Inc. ...

Page 193

... NOP NOP ; BANKSEL EEDATL MOVF EEDATL, W MOVWF DATAL MOVF EEDATH, W MOVWF DATAH © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 on the next ; ;MS Byte of Program Address to read ;LS Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ;Any instructions here are ignored as program ;memory is read in second cycle after BSF ...

Page 194

... POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 ---0 0000 ---0 0000 EEADRL0 0000 0000 0000 0000 RD 0--- x000 ---- q000 ---- ---- ---- ---- EEDATH0 --00 0000 --00 0000 EEDATL0 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...

Page 195

... Specifications” for information on PORTC). If read-write-modify instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<4> bit to be set, thus disabling the SDO output. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 FIGURE 14-1: Read SDI/SDA bit 0 ...

Page 196

... C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS41250F-page 194 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C mode only mode only mode only) R-0 R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 197

... C Firmware Controlled Master mode (slave IDLE) 1100 = Reserved 1101 = Reserved 2 1110 = I C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R/W-0 (2) (2) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...

Page 198

... SSPBUF register. Additionally, the SSP STATUS register (SSPSTAT) indicates the various status conditions. completed ; ;Has data been received(transmit complete)? ;No ; ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit © 2007 Microchip Technology Inc. ...

Page 199

... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb Processor 1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 14.4 Typical Connection Figure 14-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...

Page 200

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...

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