R5F21258SDFP Renesas Electronics Corporation., R5F21258SDFP Datasheet
R5F21258SDFP
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R5F21258SDFP Summary of contents
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REJ09B0244-0300 R8C/24 16 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. Asynchronous Communication ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Applications ............................................................................................................................................... 1 1.2 Performance Overview .............................................................................................................................. 2 1.3 Block Diagram .......................................................................................................................................... 4 1.4 Product Information .................................................................................................................................. 5 1.5 Pin Assignments ........................................................................................................................................ 9 1.6 Pin Functions ........................................................................................................................................... 11 ...
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Monitoring Vdet0 ............................................................................................................................... 40 6.1.2 Monitoring Vdet1 ............................................................................................................................... 40 6.1.3 Monitoring Vdet2 ............................................................................................................................... 40 6.2 Voltage Monitor 0 Reset ......................................................................................................................... 41 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 42 6.4 Voltage Monitor 2 Interrupt and ...
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Protection .................................................................................................................................... 100 12. Interrupts ..................................................................................................................................... 101 12.1 Interrupt Overview ................................................................................................................................ 101 12.1.1 Types of Interrupts ............................................................................................................................ 101 12.1.2 Software Interrupts ........................................................................................................................... 102 12.1.3 Special Interrupts .............................................................................................................................. 103 12.1.4 Peripheral Function Interrupt ............................................................................................................ 103 12.1.5 Interrupts and Interrupt Vectors ...
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PWM Mode ....................................................................................................................................... 213 14.3.8 Reset Synchronous PWM Mode ....................................................................................................... 226 14.3.9 Complementary PWM Mode ............................................................................................................ 236 14.3.10 PWM3 Mode ..................................................................................................................................... 250 14.3.11 Timer RD Interrupt ........................................................................................................................... 262 14.3.12 Notes on Timer RD ........................................................................................................................... 264 14.4 Timer RE ............................................................................................................................................... ...
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Hardware LIN End Processing ......................................................................................................... 380 17.5 Interrupt Requests .................................................................................................................................. 381 17.6 Notes on Hardware LIN ........................................................................................................................ 382 18. A/D Converter ............................................................................................................................. 383 18.1 One-Shot Mode ..................................................................................................................................... 387 18.2 Repeat Mode .......................................................................................................................................... 390 18.3 Sample and Hold ................................................................................................................................... 393 ...
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Notes on Timer RD ........................................................................................................................... 463 21.3.4 Notes on Timer RE ........................................................................................................................... 469 21.4 Notes on Serial Interface ....................................................................................................................... 472 21.5 Notes on Clock Synchronous Serial Interface ....................................................................................... 473 21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h 0009h 000Ah Protect Register 000Bh 000Ch Oscillation Stop ...
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Address Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control ...
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Address Register 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h ...
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R8C/24 Group, R8C/25 Group SINGLE-CHIP 16-BIT CMOS MCU 1. Overview These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series CPU core, and are packaged in a 52-pin molded-plastic LQFP or a 64-pin molded-plastic FLGA. ...
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R8C/24 Group, R8C/25 Group 1.2 Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/24 Group and Table 1.2 outlines the Functions and Specifications for R8C/25 Group. Table 1.1 Functions and Specifications for R8C/24 Group Item CPU Number of ...
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R8C/24 Group, R8C/25 Group Table 1.2 Functions and Specifications for R8C/25 Group Item CPU Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Peripheral Ports Functions LED drive ports Timers Serial interface Clock synchronous serial ...
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R8C/24 Group, R8C/25 Group 1.3 Block Diagram Figure 1.1 shows a Block Diagram. I/O ports Peripheral functions Timers Timer RA (8 bits) Timer RB (8 bits) Timer RD (16 bits × 2 channels) Timer RE (8 bits) Watchdog timer (15 ...
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R8C/24 Group, R8C/25 Group 1.4 Product Information Table 1.3 lists the Product Information for R8C/24 Group and Table 1.4 lists the Product Information for R8C/25 Group. Table 1.3 Product Information for R8C/24 Group Type No. R5F21244SNFP 16 Kbytes R5F21245SNFP 24 ...
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R8C/24 Group, R8C/25 Group Type No XXX FP NOTE: 1. Please contact Renesas Technology sales offices for the Y version. Figure 1.2 Type Number, Memory Size, and Package of R8C/24 Group Rev.3.00 ...
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... R5F21258SNFP 64 Kbytes R5F21254SNLG 16 Kbytes R5F21256SNLG 32 Kbytes R5F21254SDFP 16 Kbytes R5F21255SDFP 24 Kbytes R5F21256SDFP 32 Kbytes R5F21257SDFP 48 Kbytes R5F21258SDFP 64 Kbytes R5F21254SNXXXFP 16 Kbytes R5F21255SNXXXFP 24 Kbytes R5F21256SNXXXFP 32 Kbytes R5F21257SNXXXFP 48 Kbytes R5F21258SNXXXFP 64 Kbytes R5F21254SNXXXLG 16 Kbytes R5F21256SNXXXLG 32 Kbytes R5F21254SDXXXFP 16 Kbytes R5F21255SDXXXFP 24 Kbytes R5F21256SDXXXFP 32 Kbytes R5F21257SDXXXFP 48 Kbytes R5F21258SDXXXFP 64 Kbytes NOTE: 1 ...
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R8C/24 Group, R8C/25 Group Type No XXX FP NOTE: 1. Please contact Renesas Technology sales offices for the Y version. Figure 1.3 Type Number, Memory Size, and Package of R8C/25 Group Rev.3.00 ...
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R8C/24 Group, R8C/25 Group 1.5 Pin Assignments Figure 1.4 shows PLQP0052JA-A Package Pin Assignments (Top View). Figure 1.5 shows PTLG0064JA-A Package Pin Assignments. Pin assignments (top view P0_6/AN1 41 P0_5/AN2 42 P0_4/AN3 43 P4_2/VREF 44 P6_0/TREO 45 P6_2 ...
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R8C/24 Group, R8C/25 Group Pin assignments (top perspective view P3_3/SSI P0_1/AN6 P3_4/SDA/ P0_0/AN7 SCS MODE P4_4/XCOUT P2_7/ VCC/AVCC TRDIOD1 VSS/AVSS ...
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R8C/24 Group, R8C/25 Group 1.6 Pin Functions Table 1.5 lists Pin Functions. Table 1.5 Pin Functions Type Symbol Power supply input VCC, VSS Analog power AVCC, AVSS supply input Reset input RESET MODE MODE XIN clock input XIN XIN clock ...
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R8C/24 Group, R8C/25 Group Table 1.6 Pin Name Information by Pin Number Pin Control Pin Port Number 2 P3_5 3 P3_3 4 P3_4 5 MODE 6 XCIN P4_3 7 XCOUT P4_4 8 RESET 9 XOUT P4_7 10 VSS/AVSS 11 XIN ...
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R8C/24 Group, R8C/25 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 ...
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R8C/24 Group, R8C/25 Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order ...
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R8C/24 Group, R8C/25 Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag ...
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R8C/24 Group, R8C/25 Group 3. Memory 3.1 R8C/24 Group Figure 3 Memory Map of R8C/24 Group. The R8C/24 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning ...
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... R5F21254SDFP, R5F21254SDXXXFP, R5F21254SNLG, R5F21254SNXXXLG R5F21255SNFP, R5F21255SNXXXFP, R5F21255SDFP, R5F21255SDXXXFP R5F21256SNFP, R5F21256SNXXXFP, R5F21256SDFP, R5F21256SDXXXFP, R5F21256SNLG, R5F21256SNXXXLG R5F21257SNFP, R5F21257SNXXXFP, R5F21257SDFP, R5F21257SDXXXFP R5F21258SNFP, R5F21258SNXXXFP, R5F21258SDFP, R5F21258SDXXXFP Figure 3.2 Memory Map of R8C/25 Group Rev.3.00 Feb 29, 2008 Page 17 of 485 REJ09B0244-0300 0FFDCh Undefined instruction Watchdog timer/oscillation stop detection/voltage monitor ...
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R8C/24 Group, R8C/25 Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h ...
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R8C/24 Group, R8C/25 Group Table 4.2 SFR Information (2) Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h Timer RD0 Interrupt Control Register 0049h Timer RD1 Interrupt Control Register 004Ah Timer RE Interrupt Control Register 004Bh 004Ch 004Dh Key ...
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R8C/24 Group, R8C/25 Group Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh ...
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R8C/24 Group, R8C/25 Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 00D5h 00D6h A/D ...
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R8C/24 Group, R8C/25 Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register ...
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R8C/24 Group, R8C/25 Group Table 4.6 SFR Information (6) Address 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt ...
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R8C/24 Group, R8C/25 Group Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh ...
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R8C/24 Group, R8C/25 Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and ...
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R8C/24 Group, R8C/25 Group Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 ...
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R8C/24 Group, R8C/25 Group fOCO-S RESET pin 10 cycles or more are needed fOCO-S clock × 32 cycles Internal reset signal Start time of flash memory (CPU clock × 14 cycles) CPU clock Address (internal address signal) NOTES: 1. Hardware ...
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R8C/24 Group, R8C/25 Group 5.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all ...
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R8C/24 Group, R8C/25 Group VCC RESET Figure 5.5 Example of Hardware Reset Circuit and Operation RESET Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.3.00 Feb 29, 2008 Page 29 of ...
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R8C/24 Group, R8C/25 Group 5.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset ...
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R8C/24 Group, R8C/25 Group 5.3 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. When ...
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R8C/24 Group, R8C/25 Group 5.6 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the ...
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R8C/24 Group, R8C/25 Group 6. Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 0 reset, voltage ...
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R8C/24 Group, R8C/25 Group VCC Internal reference voltage Figure 6.1 Block Diagram of Voltage Detection Circuit Voltage detection 0 circuit VCA25 VCC + Internal - reference voltage Voltage detection 0 signal is held “H” when VCA25 bit is set to ...
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R8C/24 Group, R8C/25 Group Voltage detection 1 circuit fOCO-S VCA26 VCC + Noise filter Voltage Internal - detection reference 1 signal (Filter width: 200 ns) voltage Voltage detection 1 signal is held “H” when VCA26 bit is set to 0 ...
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R8C/24 Group, R8C/25 Group Voltage Detection Register Symbol VCA1 Bit Symbol — (b2-b0) VCA13 — (b7-b4) NOTES: 1. The VCA13 bit is enabled w ...
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R8C/24 Group, R8C/25 Group Voltage Monitor 0 Circuit Control Register Symbol VW0C Bit Symbol VW0C0 VW0C1 VW0C2 — (b3) VW0F0 VW0F1 VW0C6 VW0C7 NOTES: 1. Set the PRC3 bit in the ...
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R8C/24 Group, R8C/25 Group Voltage Monitor 1 Circuit Control Register Symbol VW1C Bit Symbol VW1C0 VW1C1 VW1C2 VW1C3 VW1F0 VW1F1 VW1C6 VW1C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/24 Group, R8C/25 Group Voltage Monitor 2 Circuit Control Register Symbol VW2C Bit Symbol VW2C0 VW2C1 VW2C2 VW2C3 VW2F0 VW2F1 VW2C6 VW2C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/24 Group, R8C/25 Group 6.1 VCC Input Voltage 6.1.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.1.2 Monitoring Vdet1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed (refer to 20. ...
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R8C/24 Group, R8C/25 Group 6.2 Voltage Monitor 0 Reset Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.9 shows an Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 ...
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R8C/24 Group, R8C/25 Group 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.10 shows an Example of Voltage Monitor 1 Interrupt ...
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R8C/24 Group, R8C/25 Group Vdet1 (1) 2.2 V VW1C3 bit VW1C2 bit When the VW1C1 bit is set to 0 (digital filter enabled) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) VW1C2 bit When ...
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R8C/24 Group, R8C/25 Group 6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.11 shows an Example of Voltage Monitor 2 Interrupt ...
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R8C/24 Group, R8C/25 Group Vdet2 (1) 2.2 V VCA13 bit VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) VW2C2 bit When ...
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R8C/24 Group, R8C/25 Group 7. Programmable I/O Ports There are 41 programmable Input/Output ports (I/O ports P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. Also, P4_6 and P4_7 can be used as input-only ports ...
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R8C/24 Group, R8C/25 Group 7.2 Effect on Peripheral Functions Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.6 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as ...
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R8C/24 Group, R8C/25 Group P0 Direction register Data bus Port latch P1_0 to P1_3 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P1_4 Direction register Output from individual peripheral function Data bus ...
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R8C/24 Group, R8C/25 Group P1_5 and P1_7 Direction register Output from individual peripheral function Port latch Data bus Input to individual peripheral function P1_6 Direction register Output from individual peripheral function Port latch Data bus Input to individual peripheral function ...
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R8C/24 Group, R8C/25 Group P3_0 and P3_1 Output from individual peripheral function Data bus P3_3, P3_4, P3_5, and P3_7 Output from individual peripheral function Data bus Input to individual peripheral function NOTE: 1. Ensure the input voltage to each port ...
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R8C/24 Group, R8C/25 Group P4_2/VREF P4_3/XCIN Direction Data bus Port latch P4_4/XCOUT Direction Data bus Port latch NOTES: 1. Ensure the input voltage to each port does not exceed VCC. 2. When CM10 = 1 or CM04 = 0, the ...
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R8C/24 Group, R8C/25 Group P4_5 Data bus INT0 and Input to individual peripheral function P4_6/XIN P4_7/XOUT NOTES: 1. Ensure the input voltage to each port does not exceed VCC. 2. When CM05 = 1, CM10 = 1, or CM13 = ...
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R8C/24 Group, R8C/25 Group P6_0 Output from individual peripheral function Data bus P6_1, P6_2, P6_3, and P6_4 Data bus P6_5 Output from individual peripheral function Data bus Input to individual peripheral function NOTE: 1. Ensure the input voltage to each ...
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R8C/24 Group, R8C/25 Group P6_6 Output from individual peripheral function Data bus P6_7 Data bus Input to individual peripheral function NOTE: 1. Ensure the input voltage to each port does not exceed VCC. Figure 7.7 Configuration of Programmable I/O Ports ...
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R8C/24 Group, R8C/25 Group MODE MODE signal input RESET RESET signal input NOTE: 1. Ensure the input voltage to each port does not exceed VCC. Figure 7.8 Configuration of I/O Pins Rev.3.00 Feb 29, 2008 Page 55 of 485 REJ09B0244-0300 ...
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R8C/24 Group, R8C/25 Group Port Pi Direction Register ( Symbol PD0 (3) PD1 PD2 PD3 PD4 PD6 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 ...
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R8C/24 Group, R8C/25 Group Pull-Up Control Register Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 NOTE: 1. When this bit is set to 1 (pulled up), the ...
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R8C/24 Group, R8C/25 Group Port Mode Register Symbol PMR Bit Symbol — (b3-b0) U1PINSEL — (b6-b5) IICSEL Figure 7.12 PMR Register Port P2 Drive Capacity Control ...
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R8C/24 Group, R8C/25 Group 7.4 Port settings Tables 7.4 to 7.47 list the port settings. Table 7.4 Port P0_0/AN7 Register PD0 Bit PD0_0 CH2 0 X Setting 1 X Value NOTE: 1. Pulled up ...
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R8C/24 Group, R8C/25 Group Table 7.9 Port P0_5/AN2 Register PD0 Bit PD0_5 CH2 0 X Setting 1 X Value NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. ...
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R8C/24 Group, R8C/25 Group Table 7.14 Port P1_2/KI2/AN10 Register PD1 KIEN Bit PD1_2 KI2EN Setting Value NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 ...
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R8C/24 Group, R8C/25 Group Table 7.18 Port P1_6/CLK0 Register PD1 Bit PD1_6 SMD2 0 X Setting 1 Value NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to ...
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R8C/24 Group, R8C/25 Group Table 7.21 Port P2_1/TRDIOB0 Register PD2 TRDOER1 Bit PD2_1 EB0 CMD1 CMD0 PWM3 Setting Value ...
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R8C/24 Group, R8C/25 Group Table 7.24 Port P2_4/TRDIOA1 Register PD2 TRDOER1 Bit PD2_4 EA1 CMD1 Setting X 0 Value NOTES: 1. Pulled up by setting the ...
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R8C/24 Group, R8C/25 Group Table 7.27 Port P2_7/TRDIOD1 Register PD2 TRDOER1 Bit PD2_7 ED1 CMD1 Setting 1 Value ...
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R8C/24 Group, R8C/25 Group Table 7.31 Port P3_4/SDA/SCS Register PD3 Bit PD3_4 CSS1 Setting Value NOTES: 1. Pulled up by setting ...
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R8C/24 Group, R8C/25 Group Table 7.35 Port P4_3/XCIN Register PD4 CM0 Bit PD4_3 CM04 Setting X 1 Value NOTE: 1. Pulled up by setting the PU10 ...
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R8C/24 Group, R8C/25 Group Table 7.38 Port P4_6/XIN Register CM1 Bit CM13 CM10 0 1 Setting 1 Value Table 7.39 Port P4_7/XOUT Register CM1 Bit CM13 CM10 0 1 Setting 1 Value 1 1 ...
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R8C/24 Group, R8C/25 Group Table 7.44 Port P6_4 Register PD6 Bit PD6_4 0 Setting Value 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1. Table 7.45 Port P6_5/CLK1 Register PD6 PMR Bit PD6_5 ...
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R8C/24 Group, R8C/25 Group 7.5 Unassigned Pin Handling Table 7.48 lists the Unassigned Pin Handling. Table 7.48 Unassigned Pin Handling Pin Name Ports P0 to P2, P3_0, P3_1, P3_3 to P3_7, P4_3 to P4_5, P6 Ports P4_6, P4_7 Port P4_2, ...
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R8C/24 Group, R8C/25 Group 8. Processor Mode 8.1 Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table ...
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R8C/24 Group, R8C/25 Group 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/24 Group and Table 9.2 lists Bus Cycles by Access Space of the ...
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R8C/24 Group, R8C/25 Group 10. Clock Generation Circuit The clock generation circuit has: • XIN clock oscillation circuit • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator Table 10.1 lists the Specifications of Clock Generation Circuit. ...
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R8C/24 Group, R8C/25 Group FRA00 XCOUT XCIN CM04 CM14 S Q CM10 = 1 (stop mode) R RESET Power-on reset Software reset S Q Interrupt request WAIT instruction R CM13 XIN XOUT CM13 CM05 CM02, CM04, CM05, CM06, CM07: Bits ...
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R8C/24 Group, R8C/25 Group System Clock Control Register Symbol CM0 Bit Symbol — (b1-b0) CM02 CM03 CM04 CM05 CM06 CM07 NOTES: 1. Set the PRC0 bit in the PRCR ...
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R8C/24 Group, R8C/25 Group System Clock Control Register Symbol CM1 Bit Symbol CM10 CM11 CM12 CM13 CM14 CM15 CM16 CM17 NOTES: 1. Set the PRC0 bit in the PRCR register to ...
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R8C/24 Group, R8C/25 Group Oscillation Stop Detection Register Symbol OCD Bit Symbol OCD0 OCD1 OCD2 OCD3 — (b7-b4) NOTES: 1. Set the PRC0 bit in the PRCR register ...
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R8C/24 Group, R8C/25 Group High-Speed On-Chip Oscillator Control Register Symbol FRA0 Bit Symbol FRA00 FRA01 — (b7-b2) NOTES: Set the PRC0 bit in the PRCR ...
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R8C/24 Group, R8C/25 Group High-Speed On-Chip Oscillator Control Register Symbol FRA2 Bit Symbol FRA20 FRA21 FRA22 — (b7-b3) NOTE: 1. Set the PRC0 bit in the ...
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R8C/24 Group, R8C/25 Group Clock Prescaler Reset Flag Symbol CPSRF Bit Symbol — (b6-b0) CPSR NOTE: 1. Only w rite 1 to this bit w ...
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R8C/24 Group, R8C/25 Group Handling procedure of internal power low consumption enabled by VCA20 bit Enter low-speed clock mode or low-speed Step (1) on-chip oscillator mode Stop XIN clock and high-speed on-chip Step (2) oscillator clock VCA20 ← 1 (internal ...
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R8C/24 Group, R8C/25 Group The clocks generated by the clock generation circuits are described below. 10.1 XIN Clock This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and ...
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R8C/24 Group, R8C/25 Group 10.2 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register. 10.2.1 Low-Speed ...
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R8C/24 Group, R8C/25 Group 10.3 XCIN Clock This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU clock, timer RA, and timer RE. The XCIN clock oscillation circuit is ...
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R8C/24 Group, R8C/25 Group 10.4 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. 10.4.1 System Clock ...
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R8C/24 Group, R8C/25 Group 10.4.9 fC4 and fC32 The clock fC4 and fC32 are used for timer RA and timer RE. Use fC4 and fC32 while the XCIN clock oscillation stabilizes. Rev.3.00 Feb 29, 2008 Page 86 of 485 REJ09B0244-0300 ...
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R8C/24 Group, R8C/25 Group 10.5 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 10.5.1 Standard Operating Mode Standard operating mode is further separated into ...
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R8C/24 Group, R8C/25 Group 10.5.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division provides the CPU clock. Set the CM06 bit to 1 (divide- by-8 mode) when transiting to high-speed on-chip oscillator ...
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R8C/24 Group, R8C/25 Group 10.5.2 Wait Mode Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, ...
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R8C/24 Group, R8C/25 Group 10.5.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or a peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral ...
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R8C/24 Group, R8C/25 Group Figure 10.12 shows the Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority ...
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R8C/24 Group, R8C/25 Group 10.5.2.5 Reducing Internal Power Consumption Internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator mode. Figure 10.13 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When ...
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R8C/24 Group, R8C/25 Group 10.5.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to ...
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R8C/24 Group, R8C/25 Group 10.5.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.14 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit ...
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R8C/24 Group, R8C/25 Group Figure 10.15 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed clock mode CM05 = 0 CM07 = ...
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R8C/24 Group, R8C/25 Group 10.6 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD ...
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R8C/24 Group, R8C/25 Group Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Oscillation stop detection ((a) or (b)) Watchdog timer Voltage monitor 1 Voltage monitor 2 ...
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R8C/24 Group, R8C/25 Group Interrupt sources judgment NO OCD3 = 1 ? (XIN clock stopped) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock) ? Set OCD1 bit to 0 (oscillation stop ...
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R8C/24 Group, R8C/25 Group 10.7 Notes on Clock Generation Circuit 10.7.1 Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to ...
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R8C/24 Group, R8C/25 Group 11. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. • ...
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R8C/24 Group, R8C/25 Group 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the Types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware NOTES: 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. 2. ...
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R8C/24 Group, R8C/25 Group 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt ...
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R8C/24 Group, R8C/25 Group 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt The oscillation stop ...
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R8C/24 Group, R8C/25 Group 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address ...
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R8C/24 Group, R8C/25 Group 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Vector Addresses Interrupt ...
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R8C/24 Group, R8C/25 Group 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ...
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R8C/24 Group, R8C/25 Group (1) Interrupt Control Register Symbol TRD0IC TRD1IC SSUIC/IICIC Bit Symbol ILVL0 ILVL1 ILVL2 IR — (b7-b4) NOTES: 1. Rew rite the interrupt control register w hen the interrupt ...
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R8C/24 Group, R8C/25 Group INTi Interrupt Control Register (i Symbol INT2IC INT1IC INT3IC INT0IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL — (b5) — (b7-b6) NOTES: 1. Only 0 ...
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R8C/24 Group, R8C/25 Group 12.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR Bit The ...
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R8C/24 Group, R8C/25 Group 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level ...
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R8C/24 Group, R8C/25 Group 12.1.6.5 Interrupt Response Time Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt ...
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R8C/24 Group, R8C/25 Group 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order ...
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R8C/24 Group, R8C/25 Group 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, ...
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R8C/24 Group, R8C/25 Group 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11. Priority level of interrupt INT3 Timer RB Timer RA INT0 INT1 UART1 receive UART0 receive A/D ...
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R8C/24 Group, R8C/25 Group 12.2 INT Interrupt 12.2.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 ...
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R8C/24 Group, R8C/25 Group _______ INT0 Input Filter Select Register Symbol INTF Bit Symbol INT0F0 INT0F1 INT1F0 INT1F1 INT2F0 INT2F1 INT3F0 INT3F1 Figure 12.13 INTF Register Rev.3.00 Feb 29, 2008 Page 116 ...
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R8C/24 Group, R8C/25 Group 12.2.2 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF register. The INTi level is sampled every ...
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R8C/24 Group, R8C/25 Group 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit ...
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R8C/24 Group, R8C/25 Group (1) Key Input Enable Register Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL NOTE: 1. The IR bit in the KUPIC register may be ...
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R8C/24 Group, R8C/25 Group 12.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register ( 1). This interrupt is used as a ...
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R8C/24 Group, R8C/25 Group Address Match Interrupt Enable Register Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address Match Interrupt Register (b23) (b19) (b16) (b15) b7 ...
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R8C/24 Group, R8C/25 Group 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I Request Sources) The timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select 2 interrupt, ...
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R8C/24 Group, R8C/25 Group As with other maskable interrupts, the timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select interrupt, and I of the I flag, IR bit, bits ILVL0 to ILVL2, ...
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R8C/24 Group, R8C/25 Group 12.6 Notes on Interrupts 12.6.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h ...
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R8C/24 Group, R8C/25 Group 12.6.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt ...
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R8C/24 Group, R8C/25 Group 12.6.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts ...
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R8C/24 Group, R8C/25 Group 13. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains ...
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R8C/24 Group, R8C/25 Group Option Function Select Register Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) LVD0ON — (b6) CSPROINI NOTES: 1. The OFS register is ...
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R8C/24 Group, R8C/25 Group Watchdog Timer Reset Register b7 b0 Symbol WDTR When 00h is w ritten before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is 7FFFh w hen count ...
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R8C/24 Group, R8C/25 Group 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode ...
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R8C/24 Group, R8C/25 Group 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out ...
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R8C/24 Group, R8C/25 Group 14. Timers The MCU has two 8-bit timers with 8-bit prescalers, two 16-bit timers, and a timer with a 4-bit counter and an 8-bit counter. The two 8-bit timers with 8-bit prescalers are timer RA and ...
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R8C/24 Group, R8C/25 Group Table 14.1 Functional Comparison of Timers Item Configuration Count Count sources Function Timer mode Pulse output mode Event counter mode Provided Pulse width measurement mode Pulse period measurement mode Programmable waveform generation mode Programmable one- shot ...
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R8C/24 Group, R8C/25 Group 14.1 Timer RA Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, ...
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R8C/24 Group, R8C/25 Group (4) Timer RA Control Register Symbol TRACR Bit Symbol TSTART TCSTF TSTOP — (b3) TEDGF TUNDF — (b7-b6) NOTES: 1. Refer to 14.1.6 Notes on Tim er RA. ...
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R8C/24 Group, R8C/25 Group (1) Timer RA Mode Register Symbol TRAMR Bit Symbol TMOD0 TMOD1 TMOD2 — (b3) TCK0 TCK1 TCK2 TCKCUT NOTE: 1. When both the TSTART and TCSTF bits in ...
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R8C/24 Group, R8C/25 Group 14.1.1 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode Specifications). Figure 14.4 shows the TRAIOC Register in Timer Mode. Table 14.2 Timer Mode Specifications Item ...
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R8C/24 Group, R8C/25 Group 14.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to ...
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R8C/24 Group, R8C/25 Group 14.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 14.3 ...
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R8C/24 Group, R8C/25 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Figure 14.6 TRAIOC Register in Pulse Output Mode Rev.3.00 ...
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R8C/24 Group, R8C/25 Group 14.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4 Event Counter Mode Specifications). Figure 14.7 shows the TRAIOC Register in Event Counter Mode. Table ...
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R8C/24 Group, R8C/25 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO pin ...
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R8C/24 Group, R8C/25 Group 14.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.8 shows ...
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R8C/24 Group, R8C/25 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/24 Group, R8C/25 Group n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh n 0000h Set program 1 TSTART bit in TRACR register 0 1 Measured pulse (TRAIO pin ...
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R8C/24 Group, R8C/25 Group 14.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.10 shows ...
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R8C/24 Group, R8C/25 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/24 Group, R8C/25 Group Underflow signal of timer RA prescaler Set program 1 TSTART bit in TRACR register 0 Starts counting 1 Measurement pulse (TRAIO pin input) 0 Contents of TRA Contents of read-out (1) buffer 1 ...
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R8C/24 Group, R8C/25 Group 14.1.6 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. • Even if the prescaler and timer RA ...
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R8C/24 Group, R8C/25 Group 14.2 Timer RB Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the Specifications of Each Mode). ...
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R8C/24 Group, R8C/25 Group Timer RB Control Register Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP — (b7-b3) NOTES: 1. Refer to 14.2.5 Notes on Tim er RB. 2. When the TSTOP bit ...
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R8C/24 Group, R8C/25 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Timer RB Mode Register Symbol ...
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R8C/24 Group, R8C/25 Group Timer RB Prescaler Register b7 b0 Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode NOTE: 1. When the TSTOP bit in the TRBCR register is set to ...
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R8C/24 Group, R8C/25 Group 14.2.1 Timer Mode In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 14.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode. ...
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R8C/24 Group, R8C/25 Group 14.2.1.1 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, ...
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R8C/24 Group, R8C/25 Group When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source Reloads register of Previous value ...
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R8C/24 Group, R8C/25 Group 14.2.2 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer ...
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R8C/24 Group, R8C/25 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode 1 TSTART ...
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R8C/24 Group, R8C/25 Group 14.2.3 Programmable One-shot Generation Mode In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.9 ...
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R8C/24 Group, R8C/25 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) NOTE: 1. Refer to 14.2.3.1 One-shot Trigger Selection. Figure 14.20 TRBIOC Register ...
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R8C/24 Group, R8C/25 Group 1 TSTART bit in TRBCR register 0 Set setting 1 to TOSST bit in TRBOCR 1 register TOSSTF bit in TRBOCR register 0 INT0 pin input Count source Timer RB prescaler underflow signal ...
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R8C/24 Group, R8C/25 Group 14.2.3.1 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count ...
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R8C/24 Group, R8C/25 Group 14.2.4 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to ...
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R8C/24 Group, R8C/25 Group Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Item Count sources Count operations Wait time One-shot pulse output time (n+1)(p+1)/fi Count start conditions Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin functions ...
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R8C/24 Group, R8C/25 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) NOTE: 1. Refer to 14.2.3.1 One-shot Trigger Selection. Figure 14.22 TRBIOC Register ...
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R8C/24 Group, R8C/25 Group 1 TSTART bit in TRBCR register 0 1 TOSSTF bit in TRBOCR register 0 INT0 pin input Count source Timer RB prescaler underflow signal Counter of timer bit in TRBIC register 0 1 ...
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R8C/24 Group, R8C/25 Group 14.2.5 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB ...
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R8C/24 Group, R8C/25 Group 14.2.5.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the ...
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R8C/24 Group, R8C/25 Group • Workaround example (b): As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by ...
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R8C/24 Group, R8C/25 Group 14.2.5.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), ...
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R8C/24 Group, R8C/25 Group 14.3 Timer RD Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins. The operation clock of timer fOCO40M. Table 14.11 lists the Timer RD Operation ...
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R8C/24 Group, R8C/25 Group Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) Register TRDOER1 TRDFCR Bit EA0 PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0 Setting 1 0 value Other than above X: can be 0 ...
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R8C/24 Group, R8C/25 Group Table 14.15 Pin Functions TRDIOD0(P2_3) Register TRDOER1 TRDFCR Bit ED0 PWM3 CMD1, CMD0 Setting value Other than above X: can change ...
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R8C/24 Group, R8C/25 Group Table 14.18 Pin Functions TRDIOC1(P2_6) Register TRDOER1 TRDFCR Bit EC1 PWM3 CMD1, CMD0 Setting value Other than above X: can change ...
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R8C/24 Group, R8C/25 Group Channel i TRDi register TRDGRAi register TRDGRBi register TRDGRCi register TRDGRDi register TRDDFi register TRDCRi register TRDIORAi register TRDIORCi register TRDSRi register TRDIERi register TRDPOCRi register TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register ...
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R8C/24 Group, R8C/25 Group 14.3.1 Count Sources The count source selection method is the same in all modes. However, in PWM3 mode, the external clock cannot be selected. Table 14.21 Count Source Selection Count Source f1, f2, f4, f8, f32 ...
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R8C/24 Group, R8C/25 Group 14.3.2 Buffer Operation The TRDGRCi ( register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi ...
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R8C/24 Group, R8C/25 Group TRDGRCi register (buffer) TRDi register TRDGRAi register TRDGRCi register (buffer) TRDIOAi output The above applies under the following conditions: • BFCi bit in the TRDMR register is set to 1 (the ...
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R8C/24 Group, R8C/25 Group 14.3.3 Synchronous Operation The TRD1 register is synchronized with the TRD0 register. • Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the ...
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R8C/24 Group, R8C/25 Group 14.3.4 Pulse Output Forced Cutoff In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji ( either ...
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R8C/24 Group, R8C/25 Group INT0 input PTO bit Figure 14.31 Pulse Output Forced Cutoff Rev.3.00 Feb 29, 2008 Page 181 of 485 REJ09B0244-0300 EA0 bit EA0 bit D Q writing value S output data output data EB0 bit EB0 bit ...
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R8C/24 Group, R8C/25 Group 14.3.5 Input Capture Function The input capture function measures the external signal width and period. The content of the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = ...
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R8C/24 Group, R8C/25 Group Table 14.23 Input Capture Function Specifications Item Count sources Count operations Count period Count start condition Count stop condition Interrupt request generation timing TRDIOA0 pin function TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pin functions INT0 pin ...