# RT8004PCP

Manufacturer Part NumberRT8004PCP
ManufacturerRichtek Technology Corporation
RT8004PCP datasheet

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## Thermal Considerations

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RT8004
The RT8004 contains an internal soft-start clamp that
gradually raises the clamp on COMP after the EN/SS pin
is pulled above 0.8V. The full current range becomes
available on COMP after 1024 switching cycles. If a longer
soft-start period is desired, the clamp on COMP can be
set externally with a resistor and capacitor on the EN/SS
pin as shown in Typical Application Circuit. The soft-start
duration can be calculated by using the following formula:
V
IN
=
T
R
x
C
x
ln(
)
SS
SS
SS
V
1.8V
IN
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% − (L1+ L2+ L3+ ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuit produce losses, two main sources usually account
for most of the losses: VDD quiescent current and I
losses. The VDD quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve
actual power lost is of no consequence.
1. The VDD quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge ΔQ moves
to ground. The resulting ΔQ/Δt is the current out
from V
DD
of V
that is typically larger than the DC bias current. In
DD
continuous mode,
I
= f(Q
+Q
)
GATECHG
T
B
where Q
and Q
are the gate charges of the internal top
T
B
and bottom switches. Both the DC bias and gate charge
www.richtek.com
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losses are proportional to V
be more pronounced at higher supply voltages.
2
2. I
R losses are calculated from the resistances of the
internal switches, RSW and external inductor R
continuous mode the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET R
(s)
R
= R
SW
The R
DS(ON)
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
and multiply the result by the square of the average output
current.
Other losses including C
losses and inductor core losses generally account for less
than 2% of the total loss.

## Thermal Considerations

In most applications, the RT8004 does not dissipate much
2
R
heat due to its high efficiency. But, in applications where
the RT8004 is running at high ambient temperature with
2
R
low supply voltage and high duty cycles, such as in
dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction temperature
reaches approximately 150°C, both power switches will
be turned off and the SW node will become high
impedance. To avoid the RT8004 from exceeding the
maximum junction temperature, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds
the maximum junction temperature of the part. The
temperature rise is given by :
T
= P
R
D
Where P
θ
is the thermal resistance from the junction of the die
JA
to the ambient temperature. The junction temperature, T
is given by :
T
= T
+ T
J
A
Where T
and thus their effects will
DD
and the duty cycle (DC) as follows :
DS(ON)
x DC + R
x (1−DC)
DS(ON)TOP
DS(ON)BOT
for both the top and bottom MOSFETs can be
2
and C
ESR dissipative
IN
OUT
x θ
JA
is the power dissipated by the regulator and
D
R
is the ambient temperature.
A
DS8004-03
September 2007
. In
L
to R
SW
L
,
J