RT8058PQW

Manufacturer Part NumberRT8058PQW
ManufacturerRichtek Technology Corporation
RT8058PQW datasheet
 
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Layout Considerations

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2
2. I
R losses are calculated from the resistances of the
internal switches, R
and external inductor R
SW
continuous mode the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET R
and the duty cycle (D) as follows :
DS(ON)
R
= R
x D + R
SW
DS(ON)TOP
DS(ON)BOT
The R
for both the top and bottom MOSFETs can be
DS(ON)
obtained from the Typical Performance Characteristics
2
curves. Thus, to obtain I
R losses, simply add R
and multiply the result by the square of the average output
current. Other losses including C
dissipative losses and inductor core losses generally
account for less than 2% of the total loss.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125 C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
= ( T
- T
) /
D(MAX)
J(MAX)
A
JA
Where T
is the maximum operation junction
J(MAX)
temperature 125 C, T
is the ambient temperature and
A
the
is the junction to ambient thermal resistance.
JA
For recommended operating conditions specification of
RT8058, where T
is the maximum junction
J(MAX)
temperature of the die and T
is the maximum ambient
A
temperature. The junction to ambient thermal resistance
is layout dependent. For WQFN-16L 3x3 packages,
JA
the thermal resistance
is 68 C/W on the standard
JA
JEDEC 51-7 four-layers thermal test board.
The maximum power dissipation at T
calculated by following formula :
P
= ( 125 C
25 C ) / 68 C/W = 1.471 W for
D(MAX)
WQFN-16L 3x3 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
resistance
. For RT8058 packages, the Figure 2 of
JA
DS8058-02 August 2007
Preliminary
derating curves allows the designer to see the effect of
. In
rising ambient temperature on the maximum power
L
allowed.
x (1 D)
to R
SW
L
and C
ESR
IN
OUT

Layout Considerations

Follow the PCB layout guidelines for optimal performance
of RT8058.
}A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
}Connect the terminal of the input capacitor(s), C
close as possible to the PVDD pin. This capacitor provides
the AC current into the internal power MOSFETs.
}LX node is with high frequency voltage swing and should
be kept small area. Keep all sensitive small-signal nodes
away from LX node to prevent stray capacitive noise pick-
up.
}Flood all unused areas on all layers with copper. Flooding
= 25 C can be
A
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PVDD, VDD, VOUT, PGND, GND, or any other
DC rail in your system).
}Connect the FB pin directly to the feedback resistors.
and thermal
J(MAX)
The resistor divider must be connected between VOUT
and GND.
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
25
50
75
Ambient Temperature (°C)
Figure 2. Derating Curves for RT8058 Package
RT8058
Four Layers PCB
100
125
150
, as
IN
www.richtek.com
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