SN74LVC1G125DBV

Manufacturer Part NumberSN74LVC1G125DBV
ManufacturerTexas Instruments, Inc.
SN74LVC1G125DBV datasheet
 


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EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
I
Feature Supports Partial-Power-Down
off
Mode Operation
Supports 5-V V
Operation
CC
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
description
This bus buffer gate is designed for 1.65-V to 5.5-V V
The SN74LVC1G125 features a single line driver with a 3-state output. The output is disabled when the
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G125 is characterized for operation from –40 C to 85 C.
logic symbol
OE
A
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SCES223C – APRIL 1999 – REVISED FEBRUARY 2000
operation.
CC
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
L
H
H
L
L
L
H
X
Z
1
EN
2
1
2
4
Y
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN74LVC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
DBV OR DCK PACKAGE
(TOP VIEW)
OE
V
1
5
CC
A
2
GND
Y
3
4
through a pullup
CC
. The I
circuitry disables the outputs,
off
off
4
Y
Copyright
2000, Texas Instruments Incorporated
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