X28HC256P-12 Intersil Corporation, X28HC256P-12 Datasheet

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X28HC256P-12

Manufacturer Part Number
X28HC256P-12
Description
Manufacturer
Intersil Corporation
Datasheet

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Part Number:
X28HC256P-12
Manufacturer:
XICOR
Quantity:
20 000
5V, Byte Alterable EEPROM
The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing
a highly reliable 5V only nonvolatile memory.
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling
the entire memory to be typically rewritten in less than 0.8
seconds. The X28HC256 also features DATA Polling and
Toggle Bit Polling, two methods of providing early end of
write detection. The X28HC256 also supports the JEDEC
standard Software Data Protection feature for protecting
against inadvertent writes during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
1,000,000 write cycles per byte and an inherent data
retention of 100 years.
Block Diagram
®
1
A
ADDRESS
INPUTS
0
TO A
Data Sheet
14
V
V
OE
WE
CE
CC
SS
LATCHES AND
LATCHES AND
1-888-INTERSIL or 1-888-468-3774
X BUFFERS
LOGIC AND
Y BUFFERS
DECODER
CONTROL
DECODER
TIMING
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Access time: 70ns
• Simple byte and page write
• Low power CMOS
• Software data protection
• High speed page write capability
• Highly reliable Direct Write
• Early end of write detection
• Pb-free plus anneal available (RoHS compliant)
- Single 5V supply
- No external high voltages or V
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
- Active: 60mA
- Standby: 500µA
- Protects data against system level inadvertent writes
- Endurance: 1,000,000 cycles
- Data retention: 100 years
- DATA polling
- Toggle bit polling
DATA INPUTS/OUTPUTS
All other trademarks mentioned are the property of their respective owners.
|
AND LATCHES
May 7, 2007
Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved
I/O BUFFERS
Intersil (and design) is a registered trademark of Intersil Americas Inc.
I/O
EEPROM
256kBIT
ARRAY
0
TO I/O
7
cell
P-P
256k, 32k x 8-Bit
X28HC256
control circuits
FN8108.2

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X28HC256P-12 Summary of contents

Page 1

Data Sheet 5V, Byte Alterable EEPROM The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The ...

Page 2

... X28HC256JZ-12* (Note) X28HC256J-12 ZRR X28HC256JI-12* X28HC256JI-12 RR X28HC256JIZ-12* (Note) X28HC256JI-12 ZRR X28HC256KI-12 X28HC256KI-12 RR X28HC256KM-12 X28HC256KM-12 RR X28HC256KMB-12 C X28HC256KMB-12 X28HC256P-12 X28HC256P-12 RR X28HC256PZ-12 (Note) X28HC256P-12 RRZ X28HC256PI-12 X28HC256PI- X28HC256 ACCESS TIME TEMP. RANGE (ns) (°C) 150 - CERDIP -55 to +125 28 Ld CERDIP MIL-STD-883 28 Ld CERDIP ...

Page 3

... X28HC256JM-90* X28HC256JM-90 RR X28HC256KM-90 X28HC256KM-90 RR X28HC256KMB-90 C X28HC256KMB-90 X28HC256P-90 X28HC256P-90 RR X28HC256PZ-90 (Note) X28HC256P-90 RRZ X28HC256PI-90 X28HC256PI-90 RR X28HC256PIZ-90 (Note) X28HC256PI-90 RRZ X28HC256S-90* X28HC256S-90 RR X28HC256SI-90* X28HC256SI-90 RR X28HC256SIZ-90 (Note) X28HC256SI-90 RRZ X28HC256SI-20T1 *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel. ...

Page 4

Pinouts X28HC256 (28 LD CERDIP, FLATPACK, PDIP, SOIC) TOP VIEW ...

Page 5

Pin Names SYMBOL DESCRIPTION Address Inputs 0 14 I/O to I/O Data Input/Output Write Enable CE Chip Enable OE Output Enable Ground Connect Device Operation Read Read operations ...

Page 6

DATA Polling I/O 7 LAST WRITE I WRITE DATA WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS COMPARE? YES X28HC256 READY ...

Page 7

The Toggle Bit I/O 6 LAST WRITE I ¬ LAST WRITE YES LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n NO COMPARE OK? YES X28C256 READY FIGURE 5. TOGGLE BIT SOFTWARE FLOW The ...

Page 8

Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence ...

Page 9

Resetting Software Data Protection V CC AAA DATA 5555 2AAA ADDRESS CE WE FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE ...

Page 10

Absolute Maximum Ratings Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C X28HC256 . . . . . . . . . ...

Page 11

Capacitance +25° 1MHz, V SYMBOL C (Note 9) Input/output capacitance I/O C (Note 9) Input capacitance IN Endurance and Data Retention PARAMETER Endurance Data retention AC Conditions of Test Input pulse levels Input rise and ...

Page 12

AC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified. PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z ...

Page 13

Write Cycle Limits PARAMETER Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery (page write only) Data ...

Page 14

CE Controlled Write Cycle ADDRESS OES DATA IN DATA OUT Page Write Cycle OE (NOTE ADDRESS (NOTE 10) I/O BYTE 0 *For each successive write within the ...

Page 15

DATA Polling Timing Diagram (Note 11) ADDRESS OEH I Toggle Bit Timing Diagram (Note 11 OEH OE HIGH Z I I/O 6 NOTE: ...

Page 16

Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -A- -D- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...

Page 17

Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) PIN (1) 0.056 (1.42) 0.042 (1.07) IDENTIFIER 0.050 (1.27) TP 0.048 (1.22 0.020 (0.51) MAX 3 PLCS 0.050 (1.27) MIN 0.025 (0.64) MIN VIEW ...

Page 18

Ceramic Pin Grid Array Package (CPGA) Typ. 0.100 (2.54) All Leads 0.660 (16.76) 0.640 (16.26) NOTE: All dimensions in inches (in parentheses in millimeters). 18 X28HC256 G28.550x650A 28 LEAD CERAMIC PIN GRID ARRAY PACKAGE ...

Page 19

Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...

Page 20

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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