89C51ED2 ATMEL Corporation, 89C51ED2 Datasheet
89C51ED2
Related parts for 89C51ED2
89C51ED2 Summary of contents
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... On-chip 1792 bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes) – 768 Bytes Selected at Reset for T89C51RD2 Compatibility • On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only) – 100K Write Cycles • Dual Data Pointer • ...
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... The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 provides 2048 bytes of EEPROM for nonvolatile data storage. In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792 bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 Mode) ...
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... INT External Bus Ctrl Timer 1 Port 0 Port 1 Port 2 Port 3 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 AT89C51RD2/ED2 (1) (1) (1) (1) (1) EEPROM* Watch PCA Timer2 Keyboard -dog (AT89C51ED2) BOOT Regulator SPI POR / PFD ROM Port4 Port 5 (1) (1) (1)( ...
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SFR Mapping AT89C51RD2/ED2 4 The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, ...
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Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low Byte DPH 83h Data Pointer High Byte Table 3. System Management ...
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Table 5. Port SFRs Mnemonic Add Name P5 D8h 8-bit Port 5 P5 C7h 8-bit Port 5 (byte addressable) Table 6. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TMOD 89h Timer/Counter 0 and 1 Modes ...
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... Table 10. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register Table 11. EEPROM data Memory SFR (AT89C51ED2 only) Mnemonic Add Name EECON D2h EEPROM Data Control 4235E–8051–04/ CCAP0H7 ...
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Table 12. SFR Mapping Bit Addressable 0/8 1/9 PI2 CH F8h XXXX XX11 0000 0000 B F0h 0000 0000 P5 bit CL addressable E8h 0000 0000 1111 1111 ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 FCON ...
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... Pin Configurations Figure 2. Pin Configurations P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI P1.0/ P1.1/T2EX/SS P1.2/ECI 3 P1.3CEX0 4 P1.4/CEX1 5 P1.5/CEX2/MISO 6 P1.6/CEX3/SCK 7 8 P1.7CEX4/MOSI RST 9 P3.0/RxD 10 AT89C51ED2 P3.1/TxD 11 PDIL40 12 P3.2/INT0 P3.3/INT1 13 14 P3.4/T0 15 P3.5/T1 16 P3.6/WR 17 P3.7/RD 18 XTAL2 19 XTAL1 20 VSS 4235E–8051–04/ RST 10 P3 ...
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... P1.2/ECI 22 P1.3/CEX0 23 P4.1 24 P1.4/CEX1 25 P4 P2.4/A12 47 P2.3/A11 46 P4.7 45 P2.2/A10 44 P2.1/A9 43 P2.0/A8 42 P4.6 41 NIC VQFP64 40 VSS 39 P4.5 38 XTAL1 37 XTAL2 36 P3.7/RD 35 P4.4 34 P3.6/WR 33 P4.3 60 P5.0 59 P2.4/A12 58 P2.3/A11 57 P4.7 56 P2.2/A10 55 P2.1/A9 54 P2.0/A8 AT89C51ED2 53 P4.6 PLCC68 52 NIC 51 VSS 50 P4.5 49 XTAL1 48 XTAL2 47 P3.7/RD 46 P4.4 45 P3.6/WR 44 P4.3 NIC: Not Internaly Connected 4235E–8051–04/04 ...
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Table 13. Pin Description Pin Number Mnemonic PLCC44 VQFP44 PLCC68 15, 14, P0 12, 11, 9, 19, 21, P1.0 - ...
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Table 13. Pin Description (Continued) Pin Number Mnemonic PLCC44 VQFP44 PLCC68 XTALA1 XTALA2 54, 55, 56, 58, P2 59, 61, 64, 65 34, ...
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Table 13. Pin Description (Continued) Pin Number Mnemonic PLCC44 VQFP44 PLCC68 ALE/PRO PSEN 4235E–8051–04/04 Type VQFP64 PDIL40 Name and Function Address Latch Enable/Program Pulse: Output pulse for latching the ...
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Port Types Figure 3. Quasi-Bidirectional Output Port Latch Data AT89C51RD2/ED2 14 AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out- put that is common on the 80C51 and most of its derivatives. This output type can be ...
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Oscillator Registers 4235E–8051–04/04 To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 14. CKRL Register CKRL – Clock Reload Register ...
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Functional Block Diagram Figure 4. Functional Oscillator Block Diagram Reset F Xtal1 OSC Osc Xtal2 :2 Prescaler Divider AT89C51RD2/ED2 16 Reload CKRL 1 8-bit 0 Prescaler-Divider X2 CKCON0 • A hardware RESET puts the prescaler divider in the following state: ...
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Enhanced Features X2 Feature Description 4235E–8051–04/04 In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new fea- tures, which are : • X2 option • Dual Data Pointer • Extended RAM • Programmable Counter Array (PCA) • Hardware Watchdog ...
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Figure 6. Mode Switching Waveforms XTAL1 XTAL1:2 X2 Bit CPU Clock STD Mode AT89C51RD2/ED2 18 F OSC X2 Mode The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods per instruction to 6 ...
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Table 16. CKCON0 Register CKCON0 - Clock Control Register (8Fh WDX2 PCAX2 Bit Bit Number Mnemonic Description 7 Reserved The values for this bit are indeterminite. Do not set this bit. Watchdog Clock (This control ...
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AT89C51RD2/ED2 20 Table 17. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - ...
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Dual Data Pointer Register (DPTR) Figure 7. Use of Dual Pointer 7 AUXR1(A2H) 4235E–8051–04/04 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the ...
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AT89C51RD2/ED2 22 Table 18. AUXR1 Register AUXR1- Auxiliary Register 1(0A2h ENBOOT Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - ...
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INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but ...
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Expanded RAM (XRAM) Figure 8. Internal and External Data Memory Address 0FFh or 6FFh XRAM 00 AT89C51RD2/ED2 24 The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51RD2/ED2 device ...
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XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0 the ...
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Registers AT89C51RD2/ED2 26 Table 19. AUXR Register AUXR - Auxiliary Register (8Eh DPU - M0 Bit Bit Number Mnemonic Description Disable Weak Pull-up 7 DPU Cleared by software to activate the permanent weak pull-up (default) Set by ...
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Reset Introduction Reset Input 4235E–8051–04/04 The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 9. Reset schematic Power Monitor Hardware Watchdog PCA Watchdog RST The Reset input can be used to force a reset pulse ...
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Reset Output AT89C51RD2/ED2 28 As detailed in Section “Hardware Watchdog Timer”, page 86, the WDT generates a 96- clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case ...
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Power Monitor Description 4235E–8051–04/04 The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power sup- ply falls below a safety threshold. This is achieved by ...
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Figure 13. Power Fail Detect Vcc Reset Vcc AT89C51RD2/ED2 30 The Power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the Figure ...
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Timer 2 Auto-reload Mode 4235E–8051–04/04 The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by ...
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Programmable Clock-output AT89C51RD2/ED2 32 Figure 14. Auto-reload Mode Up/Down Counter (DCEN = CLK PERIPH 6 In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen- erator (See Figure 15). The input clock increments ...
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Figure 15. Clock-out Mode C/ FCLK PERIPH T2 T2EX AT89C51RD2/ED2 TR2 T2CON TL2 2 TH (8-bit) (8-bit) RCAP2L RCAP2H (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 33 ...
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Registers AT89C51RD2/ED2 34 Table 20. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on ...
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Table 21. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Programmable Counter Array (PCA) AT89C51RD2/ED2 36 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as ...
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Figure 16. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle 4235E–8051–04/04 The CMOD register includes three additional bits associated with the PCA (See Figure 16 and Table 22). • The CIDL bit which allows ...
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AT89C51RD2/ED2 38 Table 22. CMOD Register CMOD - PCA Counter Mode Register (D9h CIDL WDTE - Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle ...
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Table 23. CCON Register CCON - PCA Counter Control Register (D8h Bit Bit Number Mnemonic Description PCA Counter Overflow flag Set by hardware when the counter rolls over. CF flags an interrupt if ...
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Figure 17. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 AT89C51RD2/ED2 CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 ECF PCA Modules: each one of the five compare/capture modules has ...
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Table 24 shows the CCAPMn settings for the various PCA functions. Table 24. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA ...
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AT89C51RD2/ED2 42 Table 25. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn ...
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Table 27. CCAPnL Registers ( CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) ...
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PCA Capture Mode Figure 18. PCA Capture Mode CF CR Cex.n ECOMn 16-bit Software Timer/ Compare Mode AT89C51RD2/ED2 44 To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and ...
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Figure 19. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 High Speed Output Mode 4235E–8051–04/04 CF CCF4 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/ timer ECOMn CAPPn ...
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Figure 20. PCA High Speed Output Mode Write to Reset CCA PnL Write to CCAPnH 0 1 Enable Pulse Width Modulator Mode AT89C51RD2/ED2 CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16 bit comparator CH CL PCA ...
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PCA Watchdog Timer 4235E–8051–04/04 Figure 21. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers ...
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AT89C51RD2/ED2 48 The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option ...
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Serial I/O Port Framing Error Detection 4235E–8051–04/04 The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and ...
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Automatic Address Recognition Given Address AT89C51RD2/ED2 50 Figure 24. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature ...
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Broadcast Address Reset Addresses 4235E–8051–04/04 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit 1.To commu- ...
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Registers Baud Rate Selection for UART for Mode 1 and 3 AT89C51RD2/ED2 52 Table 30. SADEN Register SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable Table 31. SADDR Register SADDR ...
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Internal Baud Rate Generator (BRG) Figure 26. Internal Baud Rate F PER BRR 4235E–8051–04/04 Table 32. Baud Rate Selection Table UART TCLK RCLK (T2CON) (T2CON) (BDRCON ...
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AT89C51RD2/ED2 54 Table 33. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1 ) Clear to reset the error state, not cleared by a valid stop ...
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UART Registers 4235E–8051–04/04 Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates F = 16. 384 MHz OSC BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 35. Example of ...
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AT89C51RD2/ED2 56 Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 39. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) ...
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Table 40. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, ...
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AT89C51RD2/ED2 58 Table 41. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode 1, ...
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Table 42. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved ...
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Keyboard Interface Interrupt Power Reduction Mode AT89C51RD2/ED2 60 The AT89C51RD2/ED2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. ...
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Registers 4235E–8051–04/04 Table 43. KBF Register KBF-Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a ...
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AT89C51RD2/ED2 62 Table 44. KBE Register KBE-Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit ...
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Table 45. KBLS Register KBLS-Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line 7. ...
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Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51RD2/ED2 64 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU ...
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Baud Rate 4235E–8051–04/04 drive the network. The Master may select each Slave device by software through port pins (Figure 30). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master ...
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Functional Description Operating Modes AT89C51RD2/ED2 66 Figure 30 shows a detailed structure of the SPI Module. Figure 30. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request ...
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Master Mode Slave Mode Transmission Formats 4235E–8051–04/04 Figure 31. Full-Duplex Master-Slave Interconnection MISO 8-bit Shift register MOSI SPI SCK Clock Generator SS VDD Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one ...
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Figure 32. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 33. Data Transmission Format (CPHA = 1) ...
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Error Conditions Mode Fault (MODF) Write Collision (WCOL) Overrun Condition SS Error Flag (SSERR) Interrupts 4235E–8051–04/04 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave ...
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Registers Serial Peripheral Control Register (SPCON) AT89C51RD2/ED2 70 Figure 35. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data ...
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Serial Peripheral Status Register (SPSTA) 4235E–8051–04/04 Bit Number Bit Mnemonic Description SPR2 SPR1 SPR0 1 1 Reset Value = 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to ...
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Serial Peripheral DATa Register (SPDAT) AT89C51RD2/ED2 72 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do ...
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Interrupt System Figure 36. Interrupt Control System INT0 TF0 INT1 TF1 PCA TF2 EXF2 KBD IT SPI IT Individual Enable 4235E–8051–04/04 The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three ...
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Registers AT89C51RD2/ED2 74 The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same as standard C52 ...
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Interrupt Sources and Vector Addresses 4235E–8051–04/04 Table 52. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard ...
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AT89C51RD2/ED2 76 Table 53. IENO Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA ...
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Table 54. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt ...
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AT89C51RD2/ED2 78 Table 55. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 56. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI interrupt Enable ...
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AT89C51RD2/ED2 80 Table 57. IPL1 Register IPL1 - Interrupt Priority Register (B2h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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Table 58. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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Power Management Introduction Idle Mode Entering Idle Mode Exiting Idle Mode Power-Down Mode AT89C51RD2/ED2 82 Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In ...
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Entering Power-Down Mode Exiting Power-Down Mode Figure 37. Power-Down Exit Waveform Using INT1:0# INT1:0# OSC Active phase 4235E–8051–04/04 the and RAM contents are preserved. The status of the Port pins during Power- SFR Down mode is detailed in Table 59. ...
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AT89C51RD2/ED2 84 pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Note: Exit from power-down by reset redefines all the RAM content. Table 59. Pin ...
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Registers 4235E–8051–04/04 Table 60. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-4 - The value read from these bits is indeterminate. Do not set these bits. General Purpose ...
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Hardware Watchdog Timer Using the WDT AT89C51RD2/ED2 86 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT ...
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WDT during Power-down and Idle 4235E–8051–04/04 Table 62. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h Bit Bit Number Mnemonic Description Reserved 5 - The value read from this ...
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ONCE Mode (ON- Chip Emulation) AT89C51RD2/ED2 88 The ONCE mode facilitates testing and debugging of systems using AT89C51RD2/ED2 without removing the circuit from the board. The ONCE mode is invoked by driving cer- tain pins of the AT89C51RD2/ED2; the ...
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Power-off Flag 4235E–8051–04/04 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could ...
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Reduced EMI Mode AT89C51RD2/ED2 90 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...
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... EEPROM Data Memory Write Data 4235E–8051–04/04 This feature is available only for the AT89C51ED2 device. The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read or write access to the EEPROM memory is done with a MOVX instruction. ...
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AT89C51RD2/ED2 92 Figure 38. Recommended EEPROM Data Write Sequence EEPROM Data Write EEPROM Data Mapping EECON = 02h (EEE=1) Exec: MOVX @DPTR, A EECON = 00h (EEE=0) Sequence EEBusy Cleared? Save & Disable IT EA= 0 Data Write DPTR= Address ...
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Read Data 4235E–8051–04/04 The following procedure is used to read the data stored in the EEPROM memory: • Check EEBUSY flag • If the user application interrupts routines use XRAM memory space: Save and disable interrupts. • Load DPTR with ...
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Registers AT89C51RD2/ED2 94 Table 66. EECON Register EECON (0D2h) EEPROM Control Register Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this ...
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Flash/EEPROM Memory Features Flash Programming and Erasure 4235E–8051–04/04 The Flash memory increases EEPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 64K bytes of program memory organized respec- tively in 512 pages of 128 bytes. This memory ...
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Flash Registers and Memory Map Hardware Register Flash Memory Lock Bits AT89C51RD2/ED2 96 The AT89C51RD2/ED2 Flash memory uses several registers for its management: • Hardware registers can only be accessed through the parallel programming modes which are handled by the ...
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Default Values Software Registers 4235E–8051–04/04 Table 68. Program Lock Bits Program Lock Bits Security Level LB0 LB1 LB2 Protection Description program lock features enabled. MOVC instruction executed from external program memory is disabled from fetching ...
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AT89C51RD2/ED2 98 Table 69. Default Values Mnemonic Definition SBV Software Boot Vector BSB Boot Status Byte SSB Software Security Byte Copy of the Manufacturer Code Copy of the Device ID #1: Family Code Copy of the Device ID #2: Memories ...
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Flash Memory Status Figure 40. Flash Memory Possible Contents FFFFh Virgin 0000h Default After ISP Memory Organization 4235E–8051–04/04 Table 71. Program Lock Bits of the SSB Program Lock Bits Security Level LB0 LB1 Protection Description program ...
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Bootloader Architecture Introduction Figure 41. Diagram Context Description Access Via Specific Protocol Access From User Application Acronyms AT89C51RD2/ED2 100 The bootloader manages communication according to a specifically defined protocol to provide the whole access and service on Flash memory. Furthermore, ...
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Functional Description External Host with Specific Protocol Communication 4235E–8051–04/04 Figure 42. Bootloader Functional Description ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process ...
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Bootloader Functionality Figure 43. Hardware conditions typical sequence during power-on. AT89C51RD2/ED2 102 The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge ...
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Boot Process Figure 44. Bootloader Process PC = 0000h User Application 4235E–8051–04/04 RESET If BLJB = 0 then ENBOOT Bit (AUXR1) is Set else ENBOOT Bit (AUXR1) is Cleared Yes (PSEN = and ALE =1 or ...
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ISP Protocol Description Physical Layer Frame Description AT89C51RD2/ED2 104 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by ...
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Functional Description Software Security Bits (SSB) 4235E–8051–04/04 The SSB protects any Flash access from ISP command. The command "Program Software Security Bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) ...
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Full Chip Erase Checksum Error Flow Description Overview Communication Initialization AT89C51RD2/ED2 106 The ISP command "Full Chip Erase" erases all user Flash memory (fills with FFh) and sets some bytes used by the bootloader at their default values: • BSB ...
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Autobaud Performances Table 74. Autobaud Performances Frequency (MHz) Baudrate (kHz) 1.8432 2400 OK 4800 OK 9600 OK 19200 OK 38400 - 57600 - 115200 - Frequency (MHz) Baudrate (kHz) 8 2400 OK 4800 OK 9600 OK 19200 OK 38400 - ...
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Figure 47. Command Flow Host Sends First Character of the Frame Sends Frame (made of 2 ASCII Characters Per Byte) Echo Analysis AT89C51RD2/ED2 108 Bootloader ":" If (not received ":") ":" Else Sends Echo and Start Reception Gets Frame, and ...
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Write/Program Commands Description Figure 48. Write/Program Flow Host Send Write Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait COMMAND_OK COMMAND FINISHED Example ...
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Blank Check Command Description Figure 49. Blank Check Flow Host Send Blank Check Command OR Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not Erased COMMAND FINISHED Example AT89C51RD2/ED2 110 Blank Check Command ’X’ & CR ...
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Display Data Description Figure 50. Display Flow Host Send Display Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Display Data All Data Read COMMAND FINISHED Note: The maximum size of block is 400h. To ...
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Read Function Description Figure 51. Read Flow Host Send Read Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED Example AT89C51RD2/ED2 112 This flow is similar for the following frames: ...
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ISP Commands Summary Table 75. ISP Commands Summary Command Command Name 00h Program Code 03h Write Function 04h Display Function 05h Read Function 07h Program EEPROM data 4235E–8051–04/04 Data[0] Data[1] 00h 20h 01h 40h 80h C0h 03h 00h 04h 00h ...
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API Call Description Process Constraints Table 76. API Call Summary Command R1 A READ MANUF ID 00h XXh READ DEVICE ID1 00h XXh READ DEVICE ID2 00h XXh READ DEVICE ID3 00h XXh ERASE BLOCK 01h XXh AT89C51RD2/ED2 114 The ...
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Table 76. API Call Summary (Continued) Command R1 A PROGRAM SSB 05h XXh New BSB PROGRAM BSB 06h value New SBV PROGRAM SBV 06h value READ SSB 07h XXh READ BSB 07h XXh READ SBV 07h XXh Number of PROGRAM ...
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Characteristics E Absolute Maximum Ratings I = industrial ........................................................- Storage Temperature .................................... - 150 C Voltage ......................................-0. 6. VVoltage on Any Pin to V ...
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=2.7V to 5.5V and MHz (both internal and external code execution =4.5V to 5.5V and ...
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AT89C51RD2/ED2 118 Figure 52. I Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 53. I Test Condition, Idle Mode RST EA (NC) ...
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AC Parameters Explanation of the AC Symbols External Program Memory Characteristics 4235E–8051–04/04 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of ...
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AT89C51RD2/ED2 120 Table 78. AC Parameters for a Fix Clock Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ Table 79. AC Parameters for a ...
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External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics 4235E–8051–04/ LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T AVLL TPLAZ PXIX ...
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AT89C51RD2/ED2 122 Table 81. AC Parameters for a Fix Clock Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Table ...
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External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode 4235E–8051–04/04 T LLWL ...
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Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AT89C51RD2/ED2 124 Table 84. AC Parameters for a Fix Clock Symbol T XLXL T QVHX T XHQX ...
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AC Testing Input/Output Waveforms Float Waveforms Clock Waveforms 4235E–8051–04/04 V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made 0. 0.1V OL For timing purposes as ...
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Figure 56. Internal Clock Signals STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST ...
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... Part Number Data EEPROM AT89C51RD2-SLSIM AT89C51RD2-RLTIM No (1) AT89C51RD2-RDTIM (1) AT89C51RD2-SMSIM AT89C51ED2-SLSIM AT89C51ED2-RLTIM AT89C51ED2-3CSIM Yes AT89C51ED2- SMSIM AT89C51ED2-RDTIM Note: 1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability. 4235E–8051–04/04 Temperature Supply Voltage Range 2.7V - 5.5V Industrial AT89C51RD2/ED2 Package Packing Product Marking ...
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Packaging Information PLCC44 AT89C51RD2/ED2 128 4235E–8051–04/04 ...
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VQFP44 4235E–8051–04/04 AT89C51RD2/ED2 129 ...
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PLCC68 AT89C51RD2/ED2 130 4235E–8051–04/04 ...
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VQFP64 4235E–8051–04/04 AT89C51RD2/ED2 131 ...
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PDIL40 AT89C51RD2/ED2 132 4235E–8051–04/04 ...
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... Added DIL40 package. 4. Added Flash write programming time specification. 1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode for Vcc = 4.5V to 5.5V and internal code execution. 2. Added PDIL40 Packaging for AT89C51ED2. 1. Improved explanations throughout the document. 1. Improved explanations throughout the document. AT89C51RD2/ED2 + 1 ...
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Table of Contents AT89C51RD2/ED2 i Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations ................................................................................ 9 Port Types ........................................................................................... 14 Oscillator ............................................................................................. 15 Registers............................................................................................................. 15 Functional Block Diagram ...................................................................................16 Enhanced Features ............................................................................. 17 ...
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Serial I/O Port ...................................................................................... 49 Framing Error Detection ..................................................................................... 49 Automatic Address Recognition.......................................................................... 50 Registers............................................................................................................. 52 Baud Rate Selection for UART for Mode 1 and 3............................................... 52 UART Registers.................................................................................................. 55 Keyboard Interface ............................................................................. 60 Registers............................................................................................................. 61 Serial Port Interface ...
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AT89C51RD2/ED2 iii Bootloader Architecture .................................................................................... 100 ISP Protocol Description ...................................................................................104 Functional Description ...................................................................................... 105 Flow Description ............................................................................................... 106 API Call Description.......................................................................................... 114 Electrical Characteristics ................................................................. 116 Absolute Maximum Ratings .............................................................................. 116 DC Parameters for Standard Voltage ...............................................................116 AC Parameters ................................................................................................. ...
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... FAX (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...