IC BUFFER QUAD LV N-INV 14TSSOP

 

74LCX126MTC

Manufacturer Part Number74LCX126MTC
DescriptionIC BUFFER QUAD LV N-INV 14TSSOP
ManufacturerFairchild Semiconductor
Series74LCX
74LCX126MTC datasheets

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Specifications of 74LCX126MTC

Logic TypeBuffer/Line Driver, Non-InvertingNumber Of Elements4
Number Of Bits Per Element1Current - Output High, Low24mA, 24mA
Voltage - Supply2 V ~ 3.6 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case14-TSSOP
Logic Family74LCXNumber Of Channels Per ChipQuad
PolarityNon-InvertingSupply Voltage (max)3.6 V
Supply Voltage (min)2 VMaximum Operating Temperature85 C
Mounting StyleSMD/SMTHigh Level Output Current- 24 mA
Input Bias Current (max)10 uALow Level Output Current24 mA
Minimum Operating Temperature- 40 CNumber Of Lines (input / Output)3
Output Type3-StatePropagation Delay Time6 ns @ 2.7 V or 5.5 ns @ 3.3 V
Logic Device TypeBuffer, Non InvertingSupply Voltage Range2V To 3.6V
Logic Case StyleTSSOPNo. Of Pins14
Operating Temperature Range-40°C To +85°CFamily TypeLCX
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
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74LCX126
Low Voltage Quad Buffer with 5V Tolerant
Inputs and Outputs
Features
5V tolerant inputs and outputs
2.3V–3.6V V
specifications provided
CC
5.5ns t
max. (V
3.3V), 10µA I
PD
CC
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA output drive (V
3.0V)
CC
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
2000V
– Machine model
100V
Leadless DQFN package
Note:
1. To ensure the high-impedance state during power up
or down, OE should be tied to V
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Package
Order Number
Number
74LCX126M
M14A
74LCX126SJ
M14D
(2)
74LCX126BQX
MLP14A
74LCX126MTC
MTC14
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2000 Fairchild Semiconductor Corporation
74LCX126 Rev. 1.5.0
General Description
The LCX126 contains four independent non-inverting
buffers with 3-STATE outputs. Each output is disabled
when the associated output-enable (OE) input is LOW.
max.
CC
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V systems to 3V systems.
(1)
The 74LCX126 is fabricated with an advanced CMOS
technology to achieve high speed operation while main-
taining CMOS low power dissipation.
through a pull-up
CC
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
February 2008
www.fairchildsemi.com

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74LCX126MTC Summary of contents

  • Page 1

    ... M14A 74LCX126SJ M14D (2) 74LCX126BQX MLP14A 74LCX126MTC MTC14 Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev ...

  • Page 2

    ... Pin Assignments for SOIC, SOP, and TSSOP (Top View) Pad Assignments for DQFN (Top Through View) Pin Description Pin Names Description A Inputs n OE Output Enable Inputs n O Outputs n ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 Logic Symbol IEEE/IEC Truth Table Inputs ...

  • Page 3

    ... CC V 2.7V–3. 2.3V–2. Free-Air Operating Temperature Input Edge Rate, V Note: 4. Unused inputs must be held HIGH or LOW. They may not float. ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 Parameter (3) GND I (4) Parameter 0.8V–2.0V Rating –0.5V to +7.0V –0.5V to +7.0V – ...

  • Page 4

    ... Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 V (V) Conditions CC 2.3– ...

  • Page 5

    ... Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 V (V) Conditions CC 3.3 C 50pF, V 3.3V 2.5 C 30pF, V 2.5V 3.3 C 50pF ...

  • Page 6

    ... Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics 1MHz, t ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 (Generic for LCX Family) includes probe and jig capacitance) L ...

  • Page 7

    ... Schematic Diagram (Generic for LCX Family) ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 7 www.fairchildsemi.com ...

  • Page 8

    ... BQX Leader (Start End) Trailer (Hub End) Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) 0.059 (1.50) ©2000 Fairchild Semiconductor Corporation 74LCX126 Rev. 1.5.0 Tape Section Number of Cavities 125 (Typ.) Carrier 3000 75 (Typ 0.512 (13.00) 0.795 (20.20) ...

  • Page 9

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 10

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 11

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 12

    ... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

  • Page 13

    ... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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