DM74ALS245ASJ Fairchild Semiconductor, DM74ALS245ASJ Datasheet

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DM74ALS245ASJ

Manufacturer Part Number
DM74ALS245ASJ
Description
IC TRANSCVR TRI-ST 8BIT 20SOP
Manufacturer
Fairchild Semiconductor
Series
74ALSr
Datasheet

Specifications of DM74ALS245ASJ

Logic Type
Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
15mA, 24mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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© 2000 Fairchild Semiconductor Corporation
DM74ALS245AWM
DM74ALS245ASJ
DM74ALS245AMSA
DM74ALS245AN
DM74ALS245A
Octal 3-STATE Bus Transceiver
General Description
This advanced low power Schottky device contains 8 pairs
of 3-STATE logic elements configured as octal bus trans-
ceivers. These circuits are designed for use in memory,
microprocessor systems and in asynchronous bidirectional
data buses. Two way communication between buses is
controlled by the (DIR) input. Data transmits either from the
A bus to the B bus or from the B bus to the A bus. Both the
driver and receiver outputs can be disabled via the (G)
enable input which causes outputs to enter the high imped-
ance mode so that the buses are effectively isolated.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MSA20
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006213
Features
Function Table
H
L
X
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Non-inverting logic output
Glitch free bus during power up and down
3-STATE outputs independently controlled on A and B
buses
Low output impedance to drive terminated transmission
lines to 133
Switching response specified into 500 /50 pF
Specified to interface with CMOS at V
PNP inputs to reduce input loading
Switching specifications guaranteed over full tempera-
ture and V
LOW Logic Level
Either HIGH or LOW Logic Level
HIGH Logic Level
Package Description
G
H
L
L
CC
Control
Inputs
range
DIR
H
X
L
September 1986
Revised February 2000
B Data to A Bus
A Data to B Bus
Operation
Hi-Z
www.fairchildsemi.com
OH
V
CC
2V

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DM74ALS245ASJ Summary of contents

Page 1

... Ordering Code: Order Number Package Number DM74ALS245AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS245ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS245AMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide ...

Page 2

Absolute Maximum Ratings Supply Voltage Input Voltage Control Inputs I/O Ports Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH ...

Page 3

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 3 www.fairchildsemi.com ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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