74LVT162245MTDX Fairchild Semiconductor, 74LVT162245MTDX Datasheet

IC TRANSCVR TRI-ST 16BIT 48TSSOP

74LVT162245MTDX

Manufacturer Part Number
74LVT162245MTDX
Description
IC TRANSCVR TRI-ST 16BIT 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVTr
Datasheet

Specifications of 74LVT162245MTDX

Logic Type
Transceiver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA; -12mA, 12mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74LVT162245G
(Note 1)(Note 2)
74LVT162245MEA
(Note 2)
74LVT162245MTD
(Note 2)
74LVTH162245G
(Note 1)(Note 2)
74LVTH162245MEA
74LVTH162245MEX
74LVTH162245MTD
74LVTH162245MTX
74LVT162245 • 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25: Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen non-
inverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT162245 and LVTH162245 are designed with
equivalent 25
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low volt-
age (3.3V) V
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining a low power dissipation.
Ordering Code:
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
CC
:
applications, but with the capability to pro-
series resistance in both the HIGH and
Package Number
(Preliminary)
BGA54A
BGA54A
MS48A
MTD48
MS48A
MS48A
MTD48
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
DS012446
Features
Input and output interface capability to systems at
5V V
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
A Port outputs include equivalent series resistance of
25
and reducing overshoot and undershoot
A Port outputs source/sink
B Port outputs source/sink
Functionally compatible with the 74 series 162245
Latch-up performance exceeds 500 mA
ESD performance:
Human-body model
Machine model
Charged-device model
Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
:
CC
making external termination resistors unnecessary
Package Description
!
200V
!
2000V
!
1000V
r

12 mA.
32 mA/
January 1999
Revised June 2005

64 mA
www.fairchildsemi.com

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74LVT162245MTDX Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation Features Input and output interface capability to systems ...

Page 2

Logic Symbol Connection Diagrams Pin Assignments for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n T/R Transmit/Receive Input n A –A Side A Inputs/3-STATE Outputs ...

Page 3

Functional Description The LVT162245 and LVTH162245 contain sixteen non- inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identi- Logic Diagrams Please note that these diagrams are provided only for the understanding of logic ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage I V Output Voltage Input Diode Current Output Diode Current Output Current Supply Current per ...

Page 5

DC Electrical Characteristics Symbol Parameter I Power Up/Down PU/PD 3-STATE Current I 3-STATE Output Leakage Current OZL I 3-STATE Output Leakage Current OZL (Note 5) I 3-STATE Output Leakage Current OZH I 3-STATE Output Leakage Current OZH (Note 5)  ...

Page 6

AC Electrical Characteristics Symbol Parameter t Propagation Delay Data to A Port Output PLH t PHL t Propagation Delay Data to B Port Output PLH t PHL t Output Enable Time for A Port Output PZH t PZL t Output ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS48A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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