HEF4050BT,653 NXP Semiconductors, HEF4050BT,653 Datasheet
HEF4050BT,653
Specifications of HEF4050BT,653
HEF4050BTD-T
HEF4050BTD-T
Related parts for HEF4050BT,653
HEF4050BT,653 Summary of contents
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HEF4050B Hex non-inverting buffers Rev. 07 — 1 December 2009 1. General description The HEF4050B provides six non-inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ ...
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... NXP Semiconductors 5. Functional diagram 001aae605 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 10, 12, 15 HEF4050B_7 Product data sheet 1A 1Y 001aae607 Fig 2. Logic diagram for one gate HEF4050B n. n. 001aae606 Description supply voltage output Rev. 07 — ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin 11, 14 n.c. 13 Functional description Table 3. Guaranteed fan-out Driven element Standard TTL Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current ...
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... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL HIGH-level output voltage | LOW-level output voltage OL I HIGH-level output current V ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t HIGH to LOW nA to nY; PHL propagation delay see t LOW to HIGH nA to nY; PLH propagation delay see t HIGH to LOW see THL output transition time t LOW to HIGH see TLH ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. Input to output propagation delays Table 9. Measurement points Input V M 0.5V DD Test data is given in Table 10. Definitions for test circuit Load capacitance including jig and probe capacitance. ...
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... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description DTL Diode Transistor Logic LOCMOS Local Oxidation CMOS TTL Transistor Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date _7 HEF4050B 20091201 • Modifications: Section 9 “Recommended operating _6 HEF4050B 20090723 _5 HEF4050B 20081111 HEF4050B_4 20080702 HEF4050B_CNV_3 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Abbreviations ...